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11. 发明申请

US20050082610A1 Metal-oxide-semiconductor device having improved performance and reliability 有权
标题翻译：具有提高的性能和可靠性的金属氧化物半导体器件
公开(公告)号：US20050082610A1
公开(公告)日：2005-04-21
申请号：US10688231
申请日：2003-10-17
申请人： Muhammed Shibib , Shuming Xu
发明人： Muhammed Shibib , Shuming Xu
IPC分类号： H01L29/78 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/76
CPC分类号： H01L29/0634 , H01L29/1083 , H01L29/402 , H01L29/407 , H01L29/4175 , H01L29/7816 , H01L29/7835
摘要： An MOS device includes a semiconductor layer comprising a substrate of a first conductivity type and a second layer of a second conductivity type formed on at least a portion of the substrate. First and second source/drain regions of the second conductivity type are formed in the second layer proximate an upper surface of the second layer, the second layer being spaced laterally from the first source/drain region. A gate is formed above the second layer proximate the upper surface of the second layer and at least partially between the first and second source/drain regions. The MOS device further includes at least one electrically conductive trench formed in the second layer between the gate and the second source/drain region, the trench being formed proximate the upper surface of the semiconductor layer and extending substantially vertically through the second layer to the substrate. The MOS device exhibits reduced HCI effects and/or improved high-frequency performance.
摘要翻译： MOS器件包括半导体层，该半导体层包括形成在衬底的至少一部分上的第一导电类型的衬底和第二导电类型的第二层。第二导电类型的第一和第二源极/漏极区域在靠近第二层的上表面的第二层中形成，第二层与第一源极/漏极区域横向隔开。栅极形成在靠近第二层的上表面的第二层上方，并且至少部分地在第一和第二源/漏区之间。 MOS器件还包括形成在栅极和第二源极/漏极区域之间的第二层中的至少一个导电沟槽，沟槽靠近半导体层的上表面形成并且基本垂直延伸穿过第二层到衬底。 MOS器件表现出降低的HCI效应和/或改善的高频性能。

12. 发明申请

US20050067655A1 Metal-oxide-semiconductor device including a buried lightly-doped drain region 失效
标题翻译：金属氧化物半导体器件包括埋入的轻掺杂漏极区域
公开(公告)号：US20050067655A1
公开(公告)日：2005-03-31
申请号：US10675633
申请日：2003-09-30
申请人： Muhammed Shibib , Shuming Xu
发明人： Muhammed Shibib , Shuming Xu
IPC分类号： H01L29/78 , H01L21/336 , H01L23/58 , H01L29/06 , H01L29/08 , H01L29/40 , H01L29/417 , H01L29/76 , H01L31/062
CPC分类号： H01L29/402 , H01L29/0615 , H01L29/0847 , H01L29/0873 , H01L29/4175 , H01L29/66659 , H01L29/7835
摘要： An MOS device includes a semiconductor layer of a first conductivity type, a source region of a second conductivity type formed in the semiconductor layer, and a drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the source region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the source and drain regions. The MOS device further includes a buried LDD region of the second conductivity type formed in the semiconductor layer between the gate and the drain region, the buried LDD region being spaced laterally from the drain region, and a second LDD region of the first conductivity type formed in the buried LDD region and proximate the upper surface of the semiconductor layer. The second LDD region is self-aligned with the gate and spaced laterally from the gate such that the gate is non-overlapping relative to the second LDD region.
摘要翻译： MOS器件包括形成在半导体层中的第一导电类型的半导体层，第二导电类型的源极区和形成在半导体层中并与源极区隔开的第二导电类型的漏极区。栅极形成在半导体层的上表面附近，并且至少部分地在源区和漏区之间形成。 MOS器件还包括形成在栅极和漏极区域之间的半导体层中的第二导电类型的埋入LDD区域，所述掩埋LDD区域与漏极区域横向间隔开，并且形成第一导电类型的第二LDD区域在掩埋的LDD区域中并且靠近半导体层的上表面。第二LDD区域与栅极自对准并且与栅极横向隔开，使得栅极相对于第二LDD区域不重叠。

13. 发明申请

US20070007593A1 METAL-OXIDE-SEMICONDUCTOR DEVICE WITH ENHANCED SOURCE ELECTRODE 审中-公开
标题翻译：具有增强源电极的金属氧化物半导体器件
公开(公告)号：US20070007593A1
公开(公告)日：2007-01-11
申请号：US11532250
申请日：2006-09-15
申请人： Frank Baiocchi , Bailey Jones , Muhammed Shibib , Shuming Xu
发明人： Frank Baiocchi , Bailey Jones , Muhammed Shibib , Shuming Xu
IPC分类号： H01L29/76
CPC分类号： H01L29/7835 , H01L29/0847 , H01L29/402 , H01L29/4175 , H01L29/456
摘要： An MOS device is formed including a semiconductor layer of a first conductivity type, a first source/drain region of a second conductivity type formed in the semiconductor layer, and a second source/drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the first source/drain region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. The MOS device further includes at least one contact, the at least one contact including a silicide layer formed on and in electrical connection with at least a portion of the first source/drain region, the silicide layer extending laterally away from the gate. The contact further includes at least one insulating layer formed directly on the silicide layer.
摘要翻译：形成MOS器件，其包括形成在半导体层中的第一导电类型的半导体层，第二导电类型的第一源极/漏极区域和形成在半导体层中的第二导电类型的第二源极/漏极区域，以及与第一源极/漏极区间隔开。栅极形成在半导体层的上表面附近并且至少部分地形成在第一和第二源/漏区之间。所述MOS器件还包括至少一个触点，所述至少一个触点包括在所述第一源极/漏极区域的至少一部分上形成并且与所述第一源极/漏极区域的至少一部分电连接的硅化物层，所述硅化物层从所述栅极横向延伸。触点还包括直接形成在硅化物层上的至少一个绝缘层。

14. 发明申请

US20060071283A1 Thick oxide region in a semiconductor device and method of forming same 失效
标题翻译：半导体器件中的厚氧化物区域及其形成方法
公开(公告)号：US20060071283A1
公开(公告)日：2006-04-06
申请号：US10953750
申请日：2004-09-29
申请人： Muhammed Shibib , Shuming Xu
发明人： Muhammed Shibib , Shuming Xu
IPC分类号： H01L29/76
CPC分类号： H01L21/76208
摘要： A method of forming an oxide region in a semiconductor device includes the steps of forming a plurality of trenches in a semiconductor layer of the device, the trenches being formed in close relative proximity to one another, and oxidizing the semiconductor layer such that an insulating layer is formed on at least sidewalls and bottom walls of the trenches. The trenches are configured such that the insulating layer formed as a result of the oxidizing step substantially fills the trenches and substantially consumes the semiconductor layer between corresponding pairs of adjacent trenches. In this manner, a substantially continuous oxide region is formed throughout the plurality of trenches.
摘要翻译：在半导体器件中形成氧化物区域的方法包括以下步骤：在器件的半导体层中形成多个沟槽，沟槽彼此相对靠近地形成，并且氧化半导体层，使得绝缘层形成在沟槽的至少侧壁和底壁上。沟槽被配置成使得由氧化步骤的结果形成的绝缘层基本上填充沟槽并且基本上消耗相应的相邻的沟槽对之间的半导体层。以这种方式，在整个多个沟槽中形成基本上连续的氧化物区域。

15. 发明申请

US20060038224A1 Metal-oxide-semiconductor device having an enhanced shielding structure 有权
公开(公告)号：US20060038224A1
公开(公告)日：2006-02-23
申请号：US10920656
申请日：2004-08-18
申请人： Muhammed Shibib , Shuming Xu
发明人： Muhammed Shibib , Shuming Xu
IPC分类号： H01L29/76
CPC分类号： H01L29/4175 , H01L29/407 , H01L29/66704 , H01L29/7816 , H01L29/7825 , H01L29/7835
摘要： An MOS device includes a semiconductor layer formed on a substrate, the substrate defining a horizontal plane and a vertical direction normal to the horizontal plane. First and second source/drain regions are formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A gate is formed proximate the upper surface of the semiconductor layer and disposed at least partially between the first and second source/drain regions. A first dielectric region is formed in the MOS device, the first dielectric region defining a trench extending downward from the upper surface of the semiconductor layer to a first distance into the semiconductor layer, the first dielectric region being formed between the first and second source/drain regions. The MOS device further includes a shielding structure formed primarily in the first dielectric region, at least a portion of the shielding structure being disposed adjacent a bottom wall of the first dielectric region and/or one or more sidewalls of the first dielectric region.

16. 发明申请

US20080093667A1 Metal-oxide-semiconductor device having trenched diffusion region and method of forming same 有权
标题翻译：具有沟槽扩散区域的金属氧化物半导体器件及其形成方法
公开(公告)号：US20080093667A1
公开(公告)日：2008-04-24
申请号：US11999168
申请日：2007-12-04
申请人： Muhammed Shibib , Shuming Xu
发明人： Muhammed Shibib , Shuming Xu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/223 , H01L21/2253 , H01L21/266 , H01L29/0653 , H01L29/0657 , H01L29/0886 , H01L29/1037 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.
摘要翻译： MOS器件包括第一导电类型的半导体层和形成在半导体层中的靠近半导体层的上表面的第二导电类型的第一和第二源极/漏极区域。第一和第二源极/漏极区域相对于彼此间隔开。至少部分地在第一和第二源极/漏极区之间形成栅极，并与半导体层电隔离。第一和第二源极/漏极区域中的至少一个被配置为具有基本上大于半导体层和给定源极/漏极区域之间的结的宽度的有效宽度。

17. 发明申请

US20060113601A1 Dual-gate metal-oxide semiconductor device 有权
标题翻译：双栅极金属氧化物半导体器件
公开(公告)号：US20060113601A1
公开(公告)日：2006-06-01
申请号：US10999705
申请日：2004-11-30
申请人： Muhammed Shibib , Shuming Xu
发明人： Muhammed Shibib , Shuming Xu
IPC分类号： H01L29/06
CPC分类号： H01L29/7835 , H01L29/402 , H01L29/7831
摘要： An MOS device includes first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A non-uniformly doped channel region of the first conductivity type is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on the upper surface of the semiconductor layer. A first gate is formed on the insulating layer at least partially between the first and second source/drain regions and above at least a portion of the channel region, and at least a second gate formed on the insulating layer above at least a portion of the channel region and between the first gate and the second source/drain region. The second gate has a length which is substantially greater than a length of the first gate, the first and second gates being electrically isolated from one another.
摘要翻译： MOS器件包括在半导体层的上表面附近形成在第二导电类型的半导体层中的第一导电类型的第一和第二源极/漏极区域，第一和第二源极/漏极区域相对于彼此间隔开。第一导电类型的非均匀掺杂沟道区形成在靠近半导体层的上表面的半导体层中，并且至少部分地在第一和第二源/漏区之间。绝缘层形成在半导体层的上表面上。至少部分地在第一和第二源极/漏极区域之间并且在沟道区域的至少一部分上方形成第一栅极，并且至少在绝缘层上形成的至少一部分第二栅极并且在第一栅极和第二源极/漏极区域之间。第二栅极的长度远大于第一栅极的长度，第一栅极和第二栅极彼此电隔离。

18. 发明申请

US20050112808A1 METAL-OXIDE-SEMICONDUCTOR DEVICE FORMED IN SILICON-ON-INSULATOR 有权
标题翻译：在绝缘体上形成的金属氧化物半导体器件
公开(公告)号：US20050112808A1
公开(公告)日：2005-05-26
申请号：US10719195
申请日：2003-11-21
申请人： Muhammed Shibib , Shuming Xu
发明人： Muhammed Shibib , Shuming Xu
IPC分类号： H01L21/336 , H01L21/84 , H01L29/417 , H01L29/76 , H01L29/78 , H01L29/786
CPC分类号： H01L29/78609 , H01L29/402 , H01L29/41741 , H01L29/66772 , H01L29/7835 , H01L29/78624 , H01L29/78645
摘要： A semiconductor device includes a substrate of a first conductivity type, an insulating layer formed on at least a portion of the substrate, and an epitaxial layer of a second conductivity type formed on at least a portion of the insulating layer. First and second source/drain regions of the second conductivity type are formed in the epitaxial layer proximate an upper surface of the epitaxial layer, the first and second source/drain regions being spaced laterally from one another. A gate is formed above the epitaxial layer proximate the upper surface of the epitaxial layer and at least partially between the first and second source/drain regions. The device further includes a first source/drain contact formed through the epitaxial layer and insulating layer, the first source/drain contact configured so as to be in direct electrical connection with the substrate, the first source/drain region and the epitaxial layer, and a second source/drain contact formed through the epitaxial layer, the second source/drain contact configured so as to be in direct electrical connection with the second source/drain region.
摘要翻译：半导体器件包括第一导电类型的衬底，形成在衬底的至少一部分上的绝缘层和形成在绝缘层的至少一部分上的第二导电类型的外延层。第二导电类型的第一和第二源极/漏极区域在接近外延层的上表面的外延层中形成，第一和第二源极/漏极区域彼此横向间隔开。栅极形成在邻近外延层的上表面的外延层的上方，并且至少部分地在第一和第二源/漏区之间。该器件还包括通过外延层和绝缘层形成的第一源极/漏极接触点，第一源极/漏极接触构造成与衬底，第一源极/漏极区域和外延层直接电连接，以及通过所述外延层形成的第二源极/漏极接触，所述第二源极/漏极接触构造成与所述第二源极/漏极区域直接电连接。

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