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11. 发明授权

US08400838B2 Semiconductor storage device and boosting circuit 有权
标题翻译：半导体存储装置和升压电路
公开(公告)号：US08400838B2
公开(公告)日：2013-03-19
申请号：US13053476
申请日：2011-03-22
申请人： Noriyasu Kumazaki , Masafumi Uemura
发明人： Noriyasu Kumazaki , Masafumi Uemura
IPC分类号： G11C16/06
CPC分类号： G11C5/145 , G11C16/30
摘要： A boosting circuit includes a clock control circuit which outputs a first reference clock signal by controlling the clock signal, and which outputs a second reference clock signal having a same period as that of the first reference clock signal, the second reference clock signal shifted in phase from the first reference clock signal. The boosting circuit includes a first pump clock generation circuit which outputs the first reference clock signal which is input thereto, as a first pump clock signal in accordance with a first pump flag signal. The boosting circuit includes a second pump clock generation circuit which outputs the second reference clock signal which is input thereto, as a second pump clock signal in accordance with a second pump flag signal. The boosting circuit includes a first charge pump which boosts an input voltage in accordance with the first pump clock signal. The boosting circuit includes a second charge pump which boosts an input voltage in accordance with the second pump clock signal.
摘要翻译：升压电路包括：时钟控制电路，其通过控制时钟信号输出第一参考时钟信号，并输出与第一参考时钟信号具有相同周期的第二参考时钟信号，第二参考时钟信号相移从第一个参考时钟信号。升压电路包括：第一泵时钟产生电路，其根据第一泵标志信号输出输入到其的第一参考时钟信号作为第一泵时钟信号。升压电路包括第二泵时钟产生电路，其根据第二泵标志信号输出输入到其的第二参考时钟信号作为第二泵时钟信号。升压电路包括第一电荷泵，其根据第一泵时钟信号升压输入电压。升压电路包括第二电荷泵，其根据第二泵时钟信号升压输入电压。

12. 发明申请

US20100214837A1 NONVOLATILE SEMICONDUCTOR MEMORY WITH CHARGE STORAGE LAYERS AND CONTROL GATES 有权
标题翻译：具有充电储存层和控制栅的非易失性半导体存储器
公开(公告)号：US20100214837A1
公开(公告)日：2010-08-26
申请号：US12552563
申请日：2009-09-02
申请人： Mario SAKO , Jun Fujimoto , Noriyasu Kumazaki , Yasuhiko Honda , Yoshihiko Kamata
发明人： Mario SAKO , Jun Fujimoto , Noriyasu Kumazaki , Yasuhiko Honda , Yoshihiko Kamata
IPC分类号： G11C16/04 , G11C11/00
CPC分类号： G11C5/147 , G11C16/0483 , G11C16/30
摘要： A nonvolatile semiconductor memory includes a memory cell array, bit lines, a first voltage generator, and a second voltage generator. The memory cell array includes memory cells. The bit lines each of which is connected electrically to one end of the current path of the corresponding one of the memory cells. The first voltage generator which is capable of supplying via a first output terminal to the bit lines a first voltage externally supplied or a third voltage which is obtained by stepping down a second voltage supplied and higher than the first voltage and which is as high as the first voltage. The second voltage generator which is capable of supplying a fourth voltage obtained by stepping down the second voltage to the bit lines via a second output terminal when the first voltage generator steps down the second voltage to generate the third voltage.
摘要翻译：非易失性半导体存储器包括存储单元阵列，位线，第一电压发生器和第二电压发生器。存储单元阵列包括存储单元。每个位线与相应的一个存储单元的电流路径的一端电连接。第一电压发生器，其能够经由第一输出端子向位线提供外部提供的第一电压或通过降低提供的并高于第一电压的第二电压而获得的第三电压，并且其与第一电压一样高第一电压。第二电压发生器，当第一电压发生器降低第二电压以产生第三电压时，能够将通过第二输出端降低第二电压而获得的第四电压提供给位线。

13. 发明授权

US06885606B2 Synchronous semiconductor memory device with a plurality of memory banks and method of controlling the same 失效
标题翻译：具有多个存储体的同步半导体存储器件及其控制方法
公开(公告)号：US06885606B2
公开(公告)日：2005-04-26
申请号：US10353271
申请日：2003-01-28
申请人： Noriyasu Kumazaki , Shigeo Ohshima , Kazuaki Kawaguchi
发明人： Noriyasu Kumazaki , Shigeo Ohshima , Kazuaki Kawaguchi
IPC分类号： G01R31/30 , G01R31/28 , G01R31/3185 , G11C7/10 , G11C8/12 , G11C11/401 , G11C29/06 , G11C8/00
CPC分类号： G11C7/1066 , G11C7/1072 , G11C8/12
摘要： A synchronous semiconductor memory device includes a plurality of memory banks which read data from memory cells and write data into the memory cells, a command decoder circuit which receives a command, detects whether the command is a read command or a write command, and, when detecting a read command or a write command, outputs a first control signal that enables a read operation or a write operation in the plurality of memory banks, bank select circuits which activate a second control signal to activate each of the memory banks, and bank timer circuits which deactivate the activated second control signal and perform control in such a manner that the timing with which the second control signal is deactivated in a test mode differs from that in a normal mode.
摘要翻译：同步半导体存储器件包括从存储器单元读取数据并将数据写入存储单元的多个存储器组，接收命令的命令解码器电路，检测该命令是读命令还是写命令，以及何时检测读取命令或写入命令，输出启用多个存储体中的读取操作或写入操作的第一控制信号，激活第二控制信号的存储体选择电路以激活每个存储体，以及存储体定时器电路，其使激活的第二控制信号去激活并执行控制，使得在测试模式中第二控制信号被去激活的定时与正常模式不同。

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