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11. 发明授权

US08373943B2 Magnetic head having a multilayer magnetic film and method for producing the same 有权
标题翻译：具有多层磁性膜的磁头及其制造方法
公开(公告)号：US08373943B2
公开(公告)日：2013-02-12
申请号：US12941953
申请日：2010-11-08
申请人： Kan Yasui , Nobuo Yoshida , Katsuro Watanabe , Norihiro Okawa
发明人： Kan Yasui , Nobuo Yoshida , Katsuro Watanabe , Norihiro Okawa
IPC分类号： G11B5/127
CPC分类号： G11B5/398 , B82Y25/00 , G01R33/093 , G01R33/098 , G11B5/02 , G11B5/1278 , G11B5/3146 , G11B5/3163 , G11B5/3906 , G11B2005/0002 , G11B2005/0024 , H01F10/3254 , H01F10/3263 , H01F10/329
摘要： According to one embodiment, a method for producing a magnetic head includes depositing a first film above a substrate, etching a pattern into the first film, depositing a second film on the etched portion of the first film, and depositing a third film above the first and second film to form a multilayer magnetic film, wherein the second film is embedded between the first and third film in a portion of the first film that is removed. In another embodiment, a differential magnetic read head includes a magnetic multilayer film comprising a stack of a first magnetic sensor film and a second magnetic sensor film which are not magnetically connected and a hard magnetic film provided on both sides in a track width direction of the magnetic multilayer film for controlling a magnetic domain of the magnetic multilayer film. The hard magnetic film is a laminated structure as described above.
摘要翻译：根据一个实施例，一种用于制造磁头的方法包括在基板上沉积第一膜，将图案蚀刻到第一膜中，在第一膜的蚀刻部分上沉积第二膜，以及在第一膜上沉积第三膜和第二膜以形成多层磁性膜，其中第二膜在被去除的第一膜的一部分中嵌入第一和第三膜之间。在另一个实施例中，差分磁读头包括磁性多层膜，该磁性多层膜包括不磁性连接的第一磁性传感器膜和第二磁性传感器膜的叠层，以及设置在第二磁性传感器膜的轨道宽度方向上的两侧的硬磁性膜用于控制磁性多层膜的磁畴的磁性多层膜。硬磁性膜是如上所述的层叠结构。

12. 发明申请

US20110116184A1 MAGNETIC HEAD HAVING A MULTILAYER MAGNETIC FILM AND METHOD FOR PRODUCING THE SAME 有权
标题翻译：具有多层磁性膜的磁头及其制造方法
公开(公告)号：US20110116184A1
公开(公告)日：2011-05-19
申请号：US12941953
申请日：2010-11-08
申请人： Kan Yasui , Nobuo Yoshida , Katsuro Watanabe , Norihiro Okawa
发明人： Kan Yasui , Nobuo Yoshida , Katsuro Watanabe , Norihiro Okawa
IPC分类号： G11B5/127 , G11B21/02 , G11B5/02
CPC分类号： G11B5/398 , B82Y25/00 , G01R33/093 , G01R33/098 , G11B5/02 , G11B5/1278 , G11B5/3146 , G11B5/3163 , G11B5/3906 , G11B2005/0002 , G11B2005/0024 , H01F10/3254 , H01F10/3263 , H01F10/329
摘要： According to one embodiment, a method for producing a magnetic head includes depositing a first film above a substrate, etching a pattern into the first film, depositing a second film on the etched portion of the first film, and depositing a third film above the first and second film to form a multilayer magnetic film, wherein the second film is embedded between the first and third film in a portion of the first film that is removed. In another embodiment, a differential magnetic read head includes a magnetic multilayer film comprising a stack of a first magnetic sensor film and a second magnetic sensor film which are not magnetically connected and a hard magnetic film provided on both sides in a track width direction of the magnetic multilayer film for controlling a magnetic domain of the magnetic multilayer film. The hard magnetic film is a laminated structure as described above.
摘要翻译：根据一个实施例，一种用于制造磁头的方法包括在基板上沉积第一膜，将图案蚀刻到第一膜中，在第一膜的蚀刻部分上沉积第二膜，以及在第一膜上沉积第三膜和第二膜以形成多层磁性膜，其中第二膜在被去除的第一膜的一部分中嵌入第一和第三膜之间。在另一个实施例中，差分磁读头包括磁性多层膜，该磁性多层膜包括不磁性连接的第一磁性传感器膜和第二磁性传感器膜的叠层，以及设置在第二磁性传感器膜的轨道宽度方向上的两侧的硬磁性膜用于控制磁性多层膜的磁畴的磁性多层膜。硬磁性膜是如上所述的层叠结构。

13. 发明授权

US08472258B2 Semiconductor nonvolatile memory device 有权
标题翻译：半导体非易失性存储器件
公开(公告)号：US08472258B2
公开(公告)日：2013-06-25
申请号：US13269425
申请日：2011-10-07
申请人： Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
发明人： Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/0425 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
摘要翻译：提供一种稳定运行半导体非易失性存储器件的操作方案。当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。因此，可以验证擦除状态，而不知道任何时变变化。此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

14. 发明授权

US08324092B2 Non-volatile semiconductor device and method of fabricating embedded non-volatile semiconductor memory device with sidewall gate 有权
标题翻译：非易失性半导体器件和制造具有侧壁栅极的嵌入式非易失性半导体存储器件的方法
公开(公告)号：US08324092B2
公开(公告)日：2012-12-04
申请号：US12652517
申请日：2010-01-05
申请人： Kan Yasui , Digh Hisamoto , Tetsuya Ishimaru , Shin-Ichiro Kimura
发明人： Kan Yasui , Digh Hisamoto , Tetsuya Ishimaru , Shin-Ichiro Kimura
IPC分类号： H01L21/00
CPC分类号： H01L27/115 , G11C16/0425 , H01L27/11568 , H01L29/42344
摘要： A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.
摘要翻译：提供一种制造非挥发性半导体存储器件的方法，其克服了由于最佳栅极高度的差异而引入的离子的渗透问题，同时形成利用侧壁结构的自对准分裂栅型存储单元和缩放MOS晶体管。形成在存储区域中形成侧壁的选择栅电极比逻辑区域中的栅电极高，使得自对准分离栅极存储单元的侧壁栅电极的高度大于在逻辑区域的栅电极。栅极电极的高度降低在栅电极形成之前的逻辑区域中进行。

15. 发明授权

US08125012B2 Non-volatile memory device with a silicon nitride charge holding film having an excess of silicon 有权
标题翻译：具有氮化硅电荷保持膜的非易失性存储器件具有过量的硅
公开(公告)号：US08125012B2
公开(公告)日：2012-02-28
申请号：US11639134
申请日：2006-12-15
申请人： Toshiyuki Mine , Kan Yasui , Tetsuya Ishimaru , Yasuhiro Shimamoto
发明人： Toshiyuki Mine , Kan Yasui , Tetsuya Ishimaru , Yasuhiro Shimamoto
IPC分类号： H01L21/336 , H01L21/31
CPC分类号： H01L29/42344 , H01L29/512 , H01L29/513 , H01L29/792 , Y10S438/954
摘要： Performance of a non-volatile semiconductor storage device which performs electron writing by hot electrons and hole erasure by hot holes is improved. A non-volatile memory cell which performs a writing operation by electrons and an erasure operation by holes has a p-type well region, isolation regions, a source region, and a drain region provided on an Si substrate. A control gate electrode is formed via a gate insulating film between the source region and the drain region. In a left-side side wall of the control gate electrode, a bottom Si oxide film, an electric charge holding film, a top Si oxide film, and a memory gate electrode are formed. The electric charge holding film is formed from an Si nitride film stoichiometrically excessively containing silicon.
摘要翻译：通过热电子进行电子写入和通过热孔进行空穴擦除的非易失性半导体存储装置的性能得到改善。通过电子执行写入操作和通过空穴的擦除操作的非易失性存储单元具有设置在Si衬底上的p型阱区域，隔离区域，源极区域和漏极区域。通过栅极绝缘膜在源极区域和漏极区域之间形成控制栅电极。在控制栅电极的左侧壁形成有底部的氧化硅膜，电荷保持膜，顶部氧化物膜和存储栅电极。电荷保持膜由化学计量过度地含有硅的氮化硅膜形成。

16. 发明申请

US20120026798A1 SEMICONDUCTOR NONVOLATILE MEMORY DEVICE 有权
标题翻译：半导体非易失性存储器件
公开(公告)号：US20120026798A1
公开(公告)日：2012-02-02
申请号：US13269425
申请日：2011-10-07
申请人： Digh HISAMOTO , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
发明人： Digh HISAMOTO , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
IPC分类号： G11C16/10
CPC分类号： G11C16/0425 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
摘要翻译：提供一种稳定运行半导体非易失性存储器件的操作方案。当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。因此，可以验证擦除状态，而不知道任何时变变化。此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

17. 发明授权

US08076709B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08076709B2
公开(公告)日：2011-12-13
申请号：US12873679
申请日：2010-09-01
申请人： Tetsuya Ishimaru , Digh Hisamoto , Kan Yasui , Shinichiro Kimura
发明人： Tetsuya Ishimaru , Digh Hisamoto , Kan Yasui , Shinichiro Kimura
IPC分类号： H01L29/792 , G11C16/04
CPC分类号： G11C16/0466 , H01L21/28282 , H01L29/66833 , H01L29/792
摘要： In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.
摘要翻译：在存储单元包括ONO膜的情况下，其包括用于电荷存储的氮化硅膜和位于氮化硅膜上方和下方的氧化膜; 在ONO电影上方的记忆门; 选择栅极，其经由ONO膜与存储栅的侧表面相邻; 位于选择门下方的栅极绝缘体; 源区; 和漏极区域，通过将BTBT产生的空穴注入氮化硅膜，同时向源极区域施加正电位，向存储栅极施加负电位，向选择栅极施加正电位，进行擦除操作，以及使电流从漏极区域流向源极区域，从而改善非易失性半导体存储器件的特性。

18. 发明授权

US08064261B2 Semiconductor nonvolatile memory device 有权
标题翻译：半导体非易失性存储器件
公开(公告)号：US08064261B2
公开(公告)日：2011-11-22
申请号：US12787158
申请日：2010-05-25
申请人： Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
发明人： Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/0425 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
摘要翻译：提供一种稳定运行半导体非易失性存储器件的操作方案。当在分裂栅结构的半导体非易失性存储器件中进行热孔注入时，使用不随时间变化的交叉点来验证热孔注入。因此，可以验证擦除状态，而不知道任何时变变化。此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

19. 发明授权

US07863131B2 Semiconductor device and manufacturing method for semiconductor device to reduce the lithography masks 有权
标题翻译：用于半导体器件的半导体器件和制造方法来减少光刻掩模
公开(公告)号：US07863131B2
公开(公告)日：2011-01-04
申请号：US11189078
申请日：2005-07-26
申请人： Kan Yasui , Digh Hisamoto , Tetsuya Ishimaru
发明人： Kan Yasui , Digh Hisamoto , Tetsuya Ishimaru
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , G11C16/0466 , H01L27/115 , H01L27/11519 , H01L27/11568 , H01L29/42344
摘要： Semiconductor device and manufacturing method for reducing the number of required lithography masks added to the nonvolatile memory in the standard CMOS process to shorten the production period and reduce costs. In a split-gate memory cell with silicided gate electrodes utilizing a sidewall structure, a separate auxiliary pattern is formed adjoining the selected gate electrodes. A contact is set on a wiring layer self-aligned by filling side-wall gates of polysilicon in the gap between the electrodes and auxiliary pattern. The contact may overlap onto the auxiliary pattern and device isolation region, in an optimal design considering the size of the occupied surface area. If the distance to the selected gate electrode is x, the ONO film deposit thickness is t, and the polysilicon film deposit thickness is d, then the auxiliary pattern may be separated just by a distance x such that x
摘要翻译：用于减少在标准CMOS工艺中添加到非易失性存储器中的所需光刻掩模的数量的半导体器件和制造方法，以缩短生产周期并降低成本。在具有利用侧壁结构的硅化栅电极的分裂栅极存储单元中，形成邻接所选择的栅电极的单独辅助图案。通过填充电极和辅助图案之间的间隙中的多晶硅的侧壁栅极，将接触设置在自对准的布线层上。考虑到占用的表面积的大小，接触可以以最佳设计重叠在辅助图案和设备隔离区域上。如果与选定的栅电极的距离为x，则ONO膜沉积厚度为t，多晶硅膜沉积厚度为d，则辅助图案可以仅分开距离x，使得x <2×（t + d ）。

20. 发明授权

US07671404B2 Fabrication method and structure of semiconductor non-volatile memory device 有权
标题翻译：半导体非易失性存储器件的制造方法和结构
公开(公告)号：US07671404B2
公开(公告)日：2010-03-02
申请号：US11589095
申请日：2006-10-30
申请人： Digh Hisamoto , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
发明人： Digh Hisamoto , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
IPC分类号： H01L29/94
CPC分类号： H01L27/11531 , H01L21/28282 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/42344 , H01L29/792
摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.
摘要翻译：提供具有良好写入/擦除特性的非易失性半导体存储器件。通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极氧化硅膜。存储器栅极通过层叠膜与选择栅极相邻。在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

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