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11. 发明授权

US07183653B2 Via including multiple electrical paths 有权
标题翻译：通过包括多个电路径
公开(公告)号：US07183653B2
公开(公告)日：2007-02-27
申请号：US10740957
申请日：2003-12-17
申请人： Todd B Myers , Nicholas R. Watts , Eric C Palmer , Renee M Defeo , Jui Min Lim
发明人： Todd B Myers , Nicholas R. Watts , Eric C Palmer , Renee M Defeo , Jui Min Lim
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/49827 , H01L2924/0002 , H05K1/115 , H05K3/064 , H05K3/403 , H05K3/4644 , H05K2201/09645 , H05K2201/09827 , H01L2924/00
摘要： A system includes a device having at least one integrated circuit. The integrated circuit further includes a first layer of conductive material, a second layer of conductive material, and a via having multiple electrical paths for interconnecting the first layer of conductive material and the second layer of conductive material. A method for forming a via includes drilling an opening to a depth to expose a first pad and a second pad, lining the opening with a conductive material, and insulating a first portion of the lining in the opening from a second portion of the lining in the opening to form a first electrical path contacting the first pad and a second electrical path contacting the second pad.
摘要翻译：一种系统包括具有至少一个集成电路的装置。集成电路还包括第一导电材料层，第二导电材料层，以及具有用于互连导电材料的第一层和第二导电材料层的多条电路的通路。用于形成通孔的方法包括将开口钻出一定深度以露出第一垫和第二垫，用导电材料衬套开口，并将开口中的衬里的第一部分与衬里的第二部分绝缘所述开口形成接触所述第一焊盘的第一电路径和与所述第二焊盘接触的第二电路径。

12. 发明授权

US06556453B2 Electronic circuit housing with trench vias and method of fabrication therefor 有权
公开(公告)号：US06556453B2
公开(公告)日：2003-04-29
申请号：US09735956
申请日：2000-12-13
申请人： David G. Figueroa , Nicholas R. Watts
发明人： David G. Figueroa , Nicholas R. Watts
IPC分类号： H05K118
CPC分类号： H01L23/5383 , H01L23/50 , H01L23/64 , H01L24/17 , H01L24/97 , H01L2224/16225 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H05K1/0231 , H05K1/185 , H01L2924/00 , H01L2224/0401
摘要： An electronic circuit package (400, FIG. 4) includes one or more trench vias (404, FIG. 4). Each trench via makes electrical contact with one or more terminals (526, FIG. 5) of a discrete device (520, FIG. 5) embedded within the package. A trench via can extend to a surface of the package, or one or more conventional vias (620, FIG. 6) formed within layers (602, FIG. 6) above or below the trench via can electrically connect the trench via, and thus the discrete device, to the surface of the package. The discrete device (520, FIG. 5) can be a capacitor, in one embodiment, providing decoupling capacitance to an integrated circuit load. Besides being implemented in a package, the trench vias also could be implemented in other types of electronic circuit housings (e.g., interposers, sockets, and printed circuit boards).

13. 发明授权

US08901724B2 Semiconductor package with embedded die and its methods of fabrication 有权
标题翻译：具有嵌入式芯片的半导体封装及其制造方法
公开(公告)号：US08901724B2
公开(公告)日：2014-12-02
申请号：US12655335
申请日：2009-12-29
申请人： John Stephen Guzek , Javier Soto Gonzalez , Nicholas R. Watts , Ravi K. Nalla
发明人： John Stephen Guzek , Javier Soto Gonzalez , Nicholas R. Watts , Ravi K. Nalla
IPC分类号： H01L23/02 , H01L23/12 , H01L23/053 , H01L23/48 , H01L23/52 , H01L29/40 , H01L23/498 , H01L21/56 , H01L25/03 , H01L21/683 , H01L23/538 , H05K1/18 , H01L25/10 , H05K3/46 , H01L23/00
CPC分类号： H01L24/11 , H01L21/56 , H01L21/568 , H01L21/6835 , H01L21/768 , H01L23/315 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/26 , H01L24/27 , H01L24/48 , H01L24/73 , H01L24/83 , H01L25/03 , H01L25/074 , H01L25/105 , H01L25/117 , H01L2221/68345 , H01L2224/03462 , H01L2224/0401 , H01L2224/11831 , H01L2224/12105 , H01L2224/13025 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/24145 , H01L2224/24227 , H01L2224/26 , H01L2224/27312 , H01L2224/2732 , H01L2224/32145 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/821 , H01L2224/83192 , H01L2224/83874 , H01L2224/92132 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/3511 , H01L2924/40252 , H01L2924/40407 , H01L2924/40501 , H05K1/185 , H05K3/4682 , H05K2201/10477 , H05K2203/0152 , H01L2924/00012 , H01L2924/00 , H01L2224/45099
摘要： Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.
摘要翻译：本发明的实施例描述了具有嵌入式管芯的半导体封装。该半导体封装包括一个包含嵌入式裸片的无芯基板。半导体封装提供管芯堆叠或封装堆叠功能。此外，本发明的实施例描述了一种使组装成本最小化的半导体封装的制造方法。

14. 发明申请

US20110215464A1 Semiconductor package with embedded die and its methods of fabrication 有权
标题翻译：具有嵌入式芯片的半导体封装及其制造方法
公开(公告)号：US20110215464A1
公开(公告)日：2011-09-08
申请号：US12655335
申请日：2009-12-29
申请人： John Stephen Guzek , Javier Soto Gonzalez , Nicholas R. Watts , Ravi K. Nalla
发明人： John Stephen Guzek , Javier Soto Gonzalez , Nicholas R. Watts , Ravi K. Nalla
IPC分类号： H01L25/07 , H01L21/60
CPC分类号： H01L24/11 , H01L21/56 , H01L21/568 , H01L21/6835 , H01L21/768 , H01L23/315 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/26 , H01L24/27 , H01L24/48 , H01L24/73 , H01L24/83 , H01L25/03 , H01L25/074 , H01L25/105 , H01L25/117 , H01L2221/68345 , H01L2224/03462 , H01L2224/0401 , H01L2224/11831 , H01L2224/12105 , H01L2224/13025 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/24145 , H01L2224/24227 , H01L2224/26 , H01L2224/27312 , H01L2224/2732 , H01L2224/32145 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/821 , H01L2224/83192 , H01L2224/83874 , H01L2224/92132 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/3511 , H01L2924/40252 , H01L2924/40407 , H01L2924/40501 , H05K1/185 , H05K3/4682 , H05K2201/10477 , H05K2203/0152 , H01L2924/00012 , H01L2924/00 , H01L2224/45099
摘要： Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.
摘要翻译：本发明的实施例描述了具有嵌入式管芯的半导体封装。该半导体封装包括一个包含嵌入式裸片的无芯基板。半导体封装提供管芯堆叠或封装堆叠功能。此外，本发明的实施例描述了一种使组装成本最小化的半导体封装的制造方法。

15. 发明授权

US07851269B2 Method of stiffening coreless package substrate 有权
公开(公告)号：US07851269B2
公开(公告)日：2010-12-14
申请号：US12378953
申请日：2009-02-19
申请人： Sriram Muthukumar , Nicholas R. Watts , John S. Guzek
发明人： Sriram Muthukumar , Nicholas R. Watts , John S. Guzek
IPC分类号： H01L21/00
CPC分类号： H01L23/49822 , H01L2224/0554 , H01L2224/05572 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H05K1/0271 , H05K3/28 , H05K3/4682 , H05K2203/0582 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Embodiments of the present invention relate to a method of stiffening a semiconductor coreless package substrate to improve rigidity and resistance against warpage. An embodiment of the method comprises disposing a sacrificial mask on a plurality of contact pads on a second level interconnect (package-to-board interconnect) side of a coreless package substrate, forming a molded stiffener around the sacrificial mask without increasing the effective thickness of the substrate, and removing the sacrificial mask to form a plurality of cavities in the molded stiffener corresponding to the contact pads. Embodiments also include plating the surface of the contact pads and the sidewalls of the cavities in the molded cavities with an electrically conductive material.

16. 发明授权

US08860205B2 Method of stiffening coreless package substrate 有权
标题翻译：无芯封装基板加强方法
公开(公告)号：US08860205B2
公开(公告)日：2014-10-14
申请号：US12857332
申请日：2010-08-16
申请人： Sriram Muthukumar , Nicholas R. Watts , John S. Guzek
发明人： Sriram Muthukumar , Nicholas R. Watts , John S. Guzek
IPC分类号： H01L23/12 , H01L23/498 , H05K3/28 , H05K1/02 , H05K3/46
CPC分类号： H01L23/49822 , H01L2224/0554 , H01L2224/05572 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H05K1/0271 , H05K3/28 , H05K3/4682 , H05K2203/0582 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Embodiments of the present invention relate to a method of stiffening a semiconductor coreless package substrate to improve rigidity and resistance against warpage. An embodiment of the method comprises disposing a sacrificial mask on a plurality of contact pads on a second level interconnect (package-to-board interconnect) side of a coreless package substrate, forming a molded stiffener around the sacrificial mask without increasing the effective thickness of the substrate, and removing the sacrificial mask to form a plurality of cavities in the molded stiffener corresponding to the contact pads. Embodiments also include plating the surface of the contact pads and the sidewalls of the cavities in the molded cavities with an electrically conductive material.
摘要翻译：本发明的实施例涉及一种加强半导体无芯封装基板以提高刚性和抗翘曲性的方法。该方法的一个实施例包括在无芯封装基板的第二级互连（封装 - 板间互连）侧上的多个接触焊盘上设置牺牲掩模，在牺牲掩模周围形成模制的加强件，而不增加有效厚度并且去除牺牲掩模以在对应于接触焊盘的模制加强件中形成多个空腔。实施例还包括用导电材料电镀接触垫的表面和模制空腔中的空腔的侧壁。

17. 发明申请

US20090057910A1 METHOD OF EMBEDDING PASSIVE COMPONENT WITHIN VIA 有权
标题翻译：嵌入式无源元件的方法
公开(公告)号：US20090057910A1
公开(公告)日：2009-03-05
申请号：US11847985
申请日：2007-08-30
申请人： Todd B. Myers , Nicholas R. Watts , Eric C. Palmer , Jui Min Lim
发明人： Todd B. Myers , Nicholas R. Watts , Eric C. Palmer , Jui Min Lim
IPC分类号： H01L29/00 , H01L23/48 , H01L23/52
CPC分类号： H01L21/76897 , H01L21/486 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/64 , H01L23/66 , H01L2223/6616 , H01L2924/0002 , H01L2924/15311 , H01L2924/1902 , H05K1/115 , H05K1/162 , H05K1/165 , H05K1/167 , H05K3/06 , H05K3/4053 , H05K3/421 , H05K2201/086 , H05K2201/09509 , H05K2201/09563 , H05K2201/0959 , H05K2201/09645 , H05K2201/09663 , H05K2201/09763 , H05K2201/09809 , H05K2201/09827 , H05K2201/09981 , Y10S257/916 , Y10T29/435 , Y10T29/49002 , Y10T29/49126 , Y10T29/4913 , Y10T29/49131 , Y10T29/49133 , Y10T29/49147 , Y10T29/49165 , H01L2924/00
摘要： A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.
摘要翻译：形成与通孔相关的器件的方法包括形成开口或通孔，并在通孔内形成至少一对导电通路。还公开了一种在其中具有一对导电路径的通孔。

18. 发明授权

US07275316B2 Method of embedding passive component within via 有权
标题翻译：无源元件嵌入通孔的方法
公开(公告)号：US07275316B2
公开(公告)日：2007-10-02
申请号：US10815464
申请日：2004-03-31
申请人： Todd B Myers , Nicholas R. Watts , Eric C Palmer , Jui Min Lim
发明人： Todd B Myers , Nicholas R. Watts , Eric C Palmer , Jui Min Lim
IPC分类号： H01K3/10
CPC分类号： H01L21/76897 , H01L21/486 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/64 , H01L23/66 , H01L2223/6616 , H01L2924/0002 , H01L2924/15311 , H01L2924/1902 , H05K1/115 , H05K1/162 , H05K1/165 , H05K1/167 , H05K3/06 , H05K3/4053 , H05K3/421 , H05K2201/086 , H05K2201/09509 , H05K2201/09563 , H05K2201/0959 , H05K2201/09645 , H05K2201/09663 , H05K2201/09763 , H05K2201/09809 , H05K2201/09827 , H05K2201/09981 , Y10S257/916 , Y10T29/435 , Y10T29/49002 , Y10T29/49126 , Y10T29/4913 , Y10T29/49131 , Y10T29/49133 , Y10T29/49147 , Y10T29/49165 , H01L2924/00
摘要： A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.
摘要翻译：形成与通孔相关的器件的方法包括形成开口或通孔，并在通孔内形成至少一对导电通路。还公开了一种在其中具有一对导电路径的通孔。

19. 发明授权

US06606237B1 Multilayer capacitor, wiring board, decoupling circuit, and high frequency circuit incorporating the same 有权
标题翻译：多层电容器，接线板，去耦电路以及并入其中的高频电路
公开(公告)号：US06606237B1
公开(公告)日：2003-08-12
申请号：US10180629
申请日：2002-06-27
申请人： Yasuyuki Naito , Masaaki Taniguchi , Yoichi Kuroda , Haruo Hori , David G. Figueroa , Jorge P. Rodriguez , Nicholas R. Watts , Nicholas L. Holmberg , Takashi Hioki
发明人： Yasuyuki Naito , Masaaki Taniguchi , Yoichi Kuroda , Haruo Hori , David G. Figueroa , Jorge P. Rodriguez , Nicholas R. Watts , Nicholas L. Holmberg , Takashi Hioki
IPC分类号： H01G4228
CPC分类号： H01G4/232 , H01L2224/16225 , H05K1/0231 , H05K1/185
摘要： A multilayer capacitor is constructed to minimize equivalent series inductance (ESL) and to achieve large capacitance. The capacitor includes first and second main go surface terminal electrodes provided on a first main surface of the main body of the multilayer capacitor. First and second side surface terminal electrodes are disposed on four side surfaces of the main body. The main body is divided into a low ESL section of the first main-surface side and a high capacitance section of the second main-surface side. In the low ESL section, in addition to first and second low ESL internal electrodes, a first conductive via-hole electrically connecting the first low ESL internal electrode to the first main surface terminal electrode and a second conductive via-hole electrically connecting the second low ESL internal electrode to the second main surface terminal electrode are provided. In the high capacitance section, in addition to first and second high capacitance internal electrodes, a first leading electrode electrically connecting the first high capacitance internal electrode to the first side surface terminal electrode and a second leading electrode electrically connecting the second high capacitance internal electrode to the second side surface terminal electrode are provided.
摘要翻译：构造了一个层叠电容器，以使等效串联电感（ESL）最小化并实现大电容。电容器包括设置在多层电容器的主体的第一主表面上的第一和第二主去往端子电极。第一和第二侧面终端电极设置在主体的四个侧表面上。主体分为第一主面侧的低ESL部和第二主面侧的高电容部。在低ESL部分中，除了第一和第二低ESL内部电极之外，还具有将第一低ESL内部电极与第一主要表面端子电极电连接的第一导电通孔和将第二低ESL内部电极电连接的第二导电通孔提供到第二主表面端子电极的ESL内部电极。在高容量部分中，除了第一和第二高电容内部电极之外，还具有将第一高容量内部电极与第一侧面端子电极电连接的第一引线电极和将第二高容量内部电极电连接到第二高容量内部电极的第二引出电极设置第二侧面终端电极。

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