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11. 发明授权

US06337506B2 Semiconductor memory device capable of performing stable operation for noise while preventing increase in chip area 失效
标题翻译：半导体存储器件能够在防止芯片面积增加的同时对噪声进行稳定的操作
公开(公告)号：US06337506B2
公开(公告)日：2002-01-08
申请号：US09116887
申请日：1998-07-16
申请人： Fukashi Morishita , Teruhiko Amano , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Takahiro Tsuruda , Mitsuya Kinoshita , Mako Kobayashi
发明人： Fukashi Morishita , Teruhiko Amano , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Takahiro Tsuruda , Mitsuya Kinoshita , Mako Kobayashi
IPC分类号： H01L2900
CPC分类号： H01L23/552 , G11C5/14 , H01L21/761 , H01L23/585 , H01L27/0203 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： A power supply circuit and an oscillation circuit or the like of noise generation sources are concentrated, and the periphery thereof is surrounded by a guard ring. Guard ring is provided to have bonding pads at least partially thereon. Guard ring is effectively provided utilizing the region below bonding pads, so that effective noise reduction is achieved while preventing increase in chip area.
摘要翻译：噪声产生源的电源电路和振荡电路等被集中，其周边被保护环包围。提供保护环以至少部分地具有接合焊盘。利用焊盘下方的区域有效地提供保护环，从而在防止芯片面积的增加的同时实现有效的降噪。

12. 发明授权

US5894448A Semiconductor memory device having hierarchy control circuit architecture of master/local control circuits permitting high speed accessing 失效
标题翻译：具有允许高速存取的主/局部控制电路的层级控制电路结构的半导体存储器件
公开(公告)号：US5894448A
公开(公告)日：1999-04-13
申请号：US944642
申请日：1997-10-06
申请人： Teruhiko Amano , Masaki Tsukude
发明人： Teruhiko Amano , Masaki Tsukude
IPC分类号： G11C11/41 , G11C5/02 , G11C5/06 , G11C11/401 , H01L21/8242 , H01L27/108 , G11C8/00
CPC分类号： G11C5/063 , G11C5/025
摘要： Memory mats provided in four regions formed by dividing a semiconductor chip are each further divided into a plurality of memory arrays along the longer side direction of the chip, row related circuits are provided between the memory arrays along the shorter side direction of the chip, and column decoders are provided along the longer side direction of the chip. An internal control signal from a master control circuit in the central part of the chip is transmitted in the central region with respect to the shorter side direction of the chip, buffer circuits are provided to an internal control signal transmission bus, and an internal signal is transmitted to the row related circuit and the column decoder by the buffer circuit. The length of the signal line to drive is shortened, and therefore the signal can be transmitted at a high speed, thus enabling high speed accessing. Thus, signal propagation delay can be reduced even if the chip size increases.
摘要翻译：设置在通过划分半导体芯片形成的四个区域中的存储器垫每个被进一步沿着芯片的较长边方向分成多个存储器阵列，行相关电路沿着芯片的较短边方向设置在存储器阵列之间，并且沿芯片的长边方向设置列解码器。来自芯片中心的主控制电路的内部控制信号相对于芯片的短边方向在中央区域传输，缓冲电路被提供给内部控制信号传输总线，内部信号为通过缓冲电路传输到行相关电路和列解码器。要驱动的信号线的长度被缩短，因此可以高速传输信号，从而实现高速访问。因此，即使芯片尺寸增加，也可以降低信号传播延迟。

13. 发明授权

US06756652B2 Semiconductor memory device with efficiently laid-out internal interconnection lines 失效
标题翻译：具有高效布线的内部互连线的半导体存储器件
公开(公告)号：US06756652B2
公开(公告)日：2004-06-29
申请号：US10455420
申请日：2003-06-06
申请人： Kenji Yano , Teruhiko Amano
发明人： Kenji Yano , Teruhiko Amano
IPC分类号： H01L2900
CPC分类号： H01L27/10882 , G11C5/063 , G11C7/14 , G11C7/18 , G11C8/14 , G11C11/4097 , G11C11/4099 , H01L21/76838 , H01L27/0207 , H01L27/10811 , H01L27/10885 , H01L27/10891
摘要： In a dummy word line region, a second metal interconnection line is arranged, and a connection between a low-resistive metal interconnection line constituting a word line arranged in a normal word line region and a lower gate electrode line is shifted. In a bit line twisting region, a memory cell gate electrode line is arranged to interconnect the gates of access transistors of memory cells, and a twisted bit line structure is implemented utilizing an upper metal interconnection line. A memory cell array region can more efficiently be used.
摘要翻译：在虚拟字线区域中，布置第二金属互连线，并且构成布置在正常字线区域中的字线的低电阻金属互连线与下栅极电极线之间的连接偏移。在位线扭转区域中，存储单元栅极电极线布置成互连存储单元的存取晶体管的栅极，并且利用上金属互连线实现扭曲的位线结构。可以更有效地使用存储单元阵列区域。

14. 发明授权

US06462999B1 Semiconductor memory device having internal data read circuit excellent in noise immunity 失效
标题翻译：具有内部数据读出电路的半导体存储器件具有优异的抗噪声能力
公开(公告)号：US06462999B1
公开(公告)日：2002-10-08
申请号：US09906649
申请日：2001-07-18
申请人： Teruhiko Amano
发明人： Teruhiko Amano
IPC分类号： G11C700
CPC分类号： G11C7/02 , G11C7/065 , G11C7/22 , G11C2207/002 , G11C2207/005 , G11C2207/2281
摘要： In the configuration of a charge confinement type sense amplifier, activation/inactivation of a charge containing gate and activation/inactivation of a sense amplifier circuit are controlled by different control signals. Thus, a layout area of the sense amplifier for reading of internal data is reduced.
摘要翻译：在电荷限制型读出放大器的结构中，含有电荷的栅极的激活/失活以及读出放大器电路的激活/失活由不同的控制信号控制。因此，用于读取内部数据的读出放大器的布局区域减小。

15. 发明授权

US06411556B1 Semiconductor memory device with improved layout and redundancy determining circuits 失效
标题翻译：具有改进的布局和冗余确定电路的半导体存储器件
公开(公告)号：US06411556B1
公开(公告)日：2002-06-25
申请号：US09667510
申请日：2000-09-22
申请人： Teruhiko Amano
发明人： Teruhiko Amano
IPC分类号： G11C2900
CPC分类号： G11C29/785 , G11C29/80
摘要： A row including a defective memory cell is replaced by a row of redundant memory cell, independently in each of a pair of memory blocks on opposing sides of a pair of row decoders 11. A redundancy determining circuit 1 for performing the replacement is provided for each memory block, and in the redundancy determining circuit 1, a plurality of fuse boxes 2 are arranged. Accordingly, as the fuses are laid-out in efficient manner, a semiconductor memory device is provided in which the circuits can be effectively arranged on the chip.
摘要翻译：包括有缺陷的存储单元的行被一行冗余存储单元替代，独立地在一对行解码器11的相对侧上的一对存储块中的每一个中。用于执行替换的冗余确定电路1用于执行替换存储块，并且在冗余确定电路1中，布置有多个熔丝盒2。因此，由于保险丝以有效的方式布置，所以提供半导体存储器件，其中电路可以有效地布置在芯片上。

16. 发明授权

US06194776B1 Semiconductor circuit device having triple-well structure in semiconductor substrate, method of fabricating the same, and mask device for fabrication of the same 失效
标题翻译：在半导体衬底中具有三重阱结构的半导体电路器件及其制造方法及其制造用掩模器件
公开(公告)号：US06194776B1
公开(公告)日：2001-02-27
申请号：US08850111
申请日：1997-05-01
申请人： Teruhiko Amano , Masaki Tsukude
发明人： Teruhiko Amano , Masaki Tsukude
IPC分类号： H01L2900
CPC分类号： H01L21/823493 , H01L21/761 , H01L29/1079 , H01L29/1087 , Y10S257/901
摘要： A semiconductor circuit device having a triple-well structure wherein a predetermined potential level is supplied to a top well without a contact region formed in the top well is disclosed. In an N-type ion implantation step for forming an N-type well region (1) in a P-type semiconductor substrate (5), a mask of a predetermined configuration is used so that ions are not implanted into a region of a portion which is to serve as a bottom portion (1B) of the well region (1). Then, the N-type well region (1) is formed which is shaped such that a portion (6) having P-type properties remains partially in the bottom portion (1B). The P-type portion (6) establishes electrical connection between a P-type well region (2) and the semiconductor substrate (5) to permit the potential applied to a contact region (4) to be supplied to the well region (2) therethrough. The portion (6) may include a plurality of portions (6) which allow uniform potential supply. This structure may be applied to basic cells of a memory cell array block.
摘要翻译：公开了一种具有三阱结构的半导体电路器件，其中将预定电位电平提供给顶部阱，而不形成在顶部阱中的接触区域。在用于在P型半导体衬底（5）中形成N型阱区（1）的N型离子注入步骤中，使用预定构造的掩模，使得离子不被注入到部分的区域中其用作井区（1）的底部（1B）。然后，形成N型阱区域（1），其形状使得具有P型特性的部分（6）部分地保留在底部（1B）中。 P型部分（6）建立P型阱区（2）和半导体衬底（5）之间的电连接，以允许施加到接触区（4）的电势被提供给阱区（2）通过。部分（6）可以包括允许均匀电势供应的多个部分（6）。该结构可以应用于存储单元阵列块的基本单元。

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