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11. 发明授权

US06894308B2 IC with comparator receiving expected and mask data from pads 有权
标题翻译： IC与比较器接收来自焊盘的预期和掩模数据
公开(公告)号：US06894308B2
公开(公告)日：2005-05-17
申请号：US10301898
申请日：2002-11-22
申请人： Lee D. Whetsel , Alan Hales
发明人： Lee D. Whetsel , Alan Hales
IPC分类号： G01R31/3185 , H01L23/58
CPC分类号： G01R31/3177 , G01R1/07342 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318547 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318566 , G01R31/318572 , G01R31/31924 , G01R31/31926
摘要： Test circuits located on semiconductor die enable a tester to scan test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal scheme whereby the tester transmits response test commands to the test circuits, using an expected data signal on one output pad and a mask data signal on another pad, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal scheme provides scan testing of die and ICs.
摘要翻译：位于半导体管芯上的测试电路使得测试者能够通过将激励和响应模式输入到多个裸片/ IC来并行扫描测试多个裸片/ IC。来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。还公开了使用响应信号方案，其中测试者使用一个输出焊盘上的期望数据信号和另一个焊盘上的掩模数据信号来向测试电路发送响应测试命令，以执行：（1）比较模具/ IC输出与期望的逻辑高电平，（2）比较芯片/ IC输出与预期的逻辑低电平，以及（3）掩模比较操作。信号方案的使用提供了芯片和IC的扫描测试。

12. 发明授权

US08375265B1 Delay fault testing using distributed clock dividers 有权
标题翻译：使用分布式时钟分频器延迟故障测试
公开(公告)号：US08375265B1
公开(公告)日：2013-02-12
申请号：US13231229
申请日：2011-09-13
申请人： Ramakrishnan Venkatasubramanian , Alan Hales , William Wallace
发明人： Ramakrishnan Venkatasubramanian , Alan Hales , William Wallace
IPC分类号： G01R31/28
CPC分类号： G01R31/31725 , G01R31/31858
摘要： In an embodiment of the invention, an integrated circuit with several clock domains bank is tested by first disabling a PLL clock and scanning test data into scan chains. Next delay fault testing (DFT) code is transmitted to each distributed clock divider on the integrated circuit. The PLL clock is then enabled to the distributed clock dividers. Selected clock dividers generate launch pulses that allow test data to be propagated from the scan chains into circuit blocks in the clock domains. Capture pulses are then generated by selected distributed clock dividers to capture test data coming form the circuit blocks into the scan chains. Next the PLL clock is disabled and the test data is scanned from the scan chains to an on-chip test control circuit.
摘要翻译：在本发明的一个实施例中，通过首先禁用PLL时钟并将测试数据扫描到扫描链中来测试具有多个时钟域组的集成电路。下一个延迟故障测试（DFT）代码被发送到集成电路上的每个分布式时钟分频器。 PLL时钟然后被使能到分布式时钟分频器。选择的时钟分频器产生启动脉冲，允许测试数据从扫描链传播到时钟域中的电路块。捕获脉冲然后由选定的分布式时钟分频器产生，以将来自电路块的测试数据捕获到扫描链中。接下来PLL时钟被禁用，测试数据从扫描链扫描到片上测试控制电路。

13. 发明申请

US20100095171A1 SCAN TESTING SYSTEM, METHOD AND APPARATUS 有权
标题翻译：扫描测试系统，方法和设备
公开(公告)号：US20100095171A1
公开(公告)日：2010-04-15
申请号：US12638441
申请日：2009-12-15
申请人： Lee D. Whetsel , Alan Hales
发明人： Lee D. Whetsel , Alan Hales
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R1/07342 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318547 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318566 , G01R31/318572 , G01R31/31924 , G01R31/31926
摘要： Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
摘要翻译：位于半导体管芯上的测试电路使得测试仪能够通过将激励和响应模式输入到多个管芯/ IC来并行地测试多个管芯/ IC。来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。还公开了使用响应信号编码方案，其中测试者使用每个测试电路的单个信号向测试电路发送响应测试命令，以执行：（1）比较管芯/ IC输出与期望的逻辑高（ 2）比较管芯/ IC输出与预期逻辑低电平，以及（3）掩模比较操作。信号编码方案的使用允许对芯片和IC进行功能测试，因为每个管芯/ IC输出所需的所有响应测试命令（即1-3以上）可以仅使用单个测试仪信号连接传输到每个管芯/ IC输出芯片/ IC输出。除功能测试外，还可以对芯片和IC进行扫描测试。

14. 发明申请

US20090089634A1 SCAN TESTING SYSTEM, METHOD AND APPARATUS 有权
标题翻译：扫描测试系统，方法和设备
公开(公告)号：US20090089634A1
公开(公告)日：2009-04-02
申请号：US12329957
申请日：2008-12-08
申请人： Lee D. Whetsel , Alan Hales
发明人： Lee D. Whetsel , Alan Hales
IPC分类号： G01R31/3185 , G06F11/267
CPC分类号： G01R31/3177 , G01R1/07342 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318547 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318566 , G01R31/318572 , G01R31/31924 , G01R31/31926
摘要： Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
摘要翻译：位于半导体管芯上的测试电路使得测试仪能够通过将激励和响应模式输入到多个管芯/ IC来并行地测试多个管芯/ IC。来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。还公开了使用响应信号编码方案，其中测试者使用每个测试电路的单个信号向测试电路发送响应测试命令，以执行：（1）比较管芯/ IC输出与期望的逻辑高（ 2）比较管芯/ IC输出与预期逻辑低电平，以及（3）掩模比较操作。信号编码方案的使用允许对芯片和IC进行功能测试，因为每个管芯/ IC输出所需的所有响应测试命令（即1-3以上）可以仅使用单个测试仪信号连接传输到每个管芯/ IC输出芯片/ IC输出。除功能测试外，还可以对芯片和IC进行扫描测试。

15. 发明申请

US20070114529A1 SCAN TESTING SYSTEM, METHOD AND APPARATUS 审中-公开
标题翻译：扫描测试系统，方法和设备
公开(公告)号：US20070114529A1
公开(公告)日：2007-05-24
申请号：US11626201
申请日：2007-01-23
申请人： Lee Whetsel , Alan Hales
发明人： Lee Whetsel , Alan Hales
IPC分类号： G01R31/26
CPC分类号： G01R31/3177 , G01R1/07342 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318547 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318566 , G01R31/318572 , G01R31/31924 , G01R31/31926
摘要： Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
摘要翻译：位于半导体管芯上的测试电路使得测试仪能够通过将激励和响应模式输入到多个管芯/ IC来并行地测试多个管芯/ IC。来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。还公开了使用响应信号编码方案，其中测试者使用每个测试电路的单个信号向测试电路发送响应测试命令，以执行：（1）比较管芯/ IC输出与期望的逻辑高（ 2）比较管芯/ IC输出与预期逻辑低电平，以及（3）掩模比较操作。信号编码方案的使用允许对芯片和IC进行功能测试，因为每个管芯/ IC输出所需的所有响应测试命令（即1-3以上）可以仅使用单个测试仪信号连接传输到每个管芯/ IC输出芯片/ IC输出。除功能测试外，还可以对芯片和IC进行扫描测试。

16. 发明申请

US20070061645A1 REGISTER FILE INITIALIZATION TO PREVENT UNKNOWN OUTPUTS DURING TEST 有权
标题翻译：注册文件初始化以在测试期间防止未知输出
公开(公告)号：US20070061645A1
公开(公告)日：2007-03-15
申请号：US11383211
申请日：2006-05-14
申请人： Alan Hales
发明人： Alan Hales
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A system and method for initializing a register file during a test period for an integrated circuit, wherein the register file has one or more input ports. A counter, when enabled, is initialized and counts at each write cycle of the register file and outputs a current count value to the input ports of the register file to pre-load the register file to a known state.
摘要翻译：一种用于在集成电路的测试周期期间初始化寄存器堆的系统和方法，其中所述寄存器文件具有一个或多个输入端口。计数器在使能时被初始化并在寄存器文件的每个写入周期进行计数，并将当前计数值输出到寄存器文件的输入端口，以将寄存器文件预加载到已知状态。

17. 发明授权

US07183570B2 IC with comparator receiving expected and mask data from pads 有权
标题翻译： IC与比较器接收来自焊盘的预期和掩模数据
公开(公告)号：US07183570B2
公开(公告)日：2007-02-27
申请号：US11103781
申请日：2005-04-11
申请人： Lee D. Whetsel , Alan Hales
发明人： Lee D. Whetsel , Alan Hales
IPC分类号： H01L23/58
CPC分类号： G01R31/3177 , G01R1/07342 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318547 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318566 , G01R31/318572 , G01R31/31924 , G01R31/31926
摘要： Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. The response patterns include one of expected data and mask data input on an output pad of the die/IC and the other of expected data and mask data input on another pad of the die/IC, which may be an input pad or an output pad. In addition to functional testing, scan testing of die and ICs is also possible.
摘要翻译：位于半导体管芯上的测试电路使得测试仪能够通过将激励和响应模式输入到多个管芯/ IC来并行地测试多个管芯/ IC。来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。响应模式包括在芯片/ IC的输出焊盘上输入的预期数据和掩模数据之一，以及输入到芯片/ IC的另一个焊盘上的预期数据和掩模数据中的另一个，其可以是输入焊盘或输出焊盘。除功能测试外，还可以对芯片和IC进行扫描测试。

18. 发明授权

US08604475B2 IC dies with serarate connections to expected and mask data 有权
标题翻译： IC死亡与预期和掩模数据的serarate连接
公开(公告)号：US08604475B2
公开(公告)日：2013-12-10
申请号：US13629854
申请日：2012-09-28
申请人： Lee D. Whetsel , Alan Hales
发明人： Lee D. Whetsel , Alan Hales
IPC分类号： H01L23/58
CPC分类号： G01R31/3177 , G01R1/07342 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318547 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318566 , G01R31/318572 , G01R31/31924 , G01R31/31926
摘要： Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
摘要翻译：位于半导体管芯上的测试电路使得测试仪能够通过将激励和响应模式输入到多个管芯/ IC来并行地测试多个管芯/ IC。来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。还公开了使用响应信号编码方案，其中测试者使用每个测试电路的单个信号向测试电路发送响应测试命令，以执行：（1）比较管芯/ IC输出与期望的逻辑高（ 2）比较管芯/ IC输出与预期逻辑低电平，以及（3）掩模比较操作。信号编码方案的使用允许对芯片和IC进行功能测试，因为每个管芯/ IC输出所需的所有响应测试命令（即1-3以上）可以仅使用单个测试仪信号连接传输到每个管芯/ IC输出芯片/ IC输出。除功能测试外，还可以对芯片和IC进行扫描测试。

19. 发明授权

US08299464B2 Comparator receiving expected and mask data from circuit pads 有权
标题翻译：比较器从电路板接收预期和掩模数据
公开(公告)号：US08299464B2
公开(公告)日：2012-10-30
申请号：US12911424
申请日：2010-10-25
申请人： Lee D. Whetsel , Alan Hales
发明人： Lee D. Whetsel , Alan Hales
IPC分类号： H01L23/58
CPC分类号： G01R31/3177 , G01R1/07342 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318547 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318566 , G01R31/318572 , G01R31/31924 , G01R31/31926
摘要： Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
摘要翻译：位于半导体管芯上的测试电路使得测试仪能够通过将激励和响应模式输入到多个管芯/ IC来并行地测试多个管芯/ IC。来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。还公开了使用响应信号编码方案，其中测试者使用每个测试电路的单个信号向测试电路发送响应测试命令，以执行：（1）比较管芯/ IC输出与期望的逻辑高（ 2）比较管芯/ IC输出与预期逻辑低电平，以及（3）掩模比较操作。信号编码方案的使用允许对芯片和IC进行功能测试，因为每个管芯/ IC输出所需的所有响应测试命令（即1-3以上）可以仅使用单个测试仪信号连接传输到每个管芯/ IC输出芯片/ IC输出。除功能测试外，还可以对芯片和IC进行扫描测试。

20. 发明授权

US07491970B2 IC with comparator receiving expected and mask data from pads 有权
标题翻译： IC与比较器接收来自焊盘的预期和掩模数据
公开(公告)号：US07491970B2
公开(公告)日：2009-02-17
申请号：US11971561
申请日：2008-01-09
申请人： Lee D. Whetsel , Alan Hales
发明人： Lee D. Whetsel , Alan Hales
IPC分类号： H01L23/58 , G01R31/26
CPC分类号： G01R31/3177 , G01R1/07342 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318547 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318566 , G01R31/318572 , G01R31/31924 , G01R31/31926
摘要： Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
摘要翻译：位于半导体管芯上的测试电路使得测试仪能够通过将激励和响应模式输入到多个管芯/ IC来并行地测试多个管芯/ IC。来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。还公开了使用响应信号编码方案，其中测试者使用每个测试电路的单个信号向测试电路发送响应测试命令，以执行：（1）比较管芯/ IC输出与期望的逻辑高（ 2）比较管芯/ IC输出与预期逻辑低电平，以及（3）掩模比较操作。信号编码方案的使用允许对芯片和IC进行功能测试，因为每个管芯/ IC输出所需的所有响应测试命令（即1-3以上）可以仅使用单个测试仪信号连接传输到每个管芯/ IC输出芯片/ IC输出。除功能测试外，还可以对芯片和IC进行扫描测试。

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