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    • 12. 发明授权
      US5615151A Semiconductor integrated circuit operable and programmable at multiple voltage levels 失效
    • Semiconductor integrated circuit operable and programmable at multiple voltage levels
    • 半导体集成电路在多个电压电平下可操作和可编程
    • US5615151A
    • 1997-03-25
    • US478334
    • 1995-06-07
    • Takeshi Furuno , Yasuhiro Nakamura , Akinori Matsuo
    • Takeshi Furuno , Yasuhiro Nakamura , Akinori Matsuo
    • G11C17/00 , G11C5/14 , G11C16/06 , G11C8/00
    • G11C5/143
    • Any one of the internal circuits of a semiconductor integrated circuit is made to operate both at a relatively high operating voltage having a predetermined allowable range and at a relatively low operating voltage also having a predetermined allowable range. The operating voltage is supplied from the outside. Moreover, the operating conditions of the internal circuits constituting the semiconductor integrated circuit are individually set restrictive to the relatively high operating voltage having a predetermined allowable range and to the relatively low operating voltage having a predetermined allowable range. The semiconductor integrated circuit is made to operate selectively at these operating voltages. Since the internal circuits are operated at these two kinds of operating voltages, an arrangement of internal circuits can be simplified and at the same time the semiconductor integrated circuit is usable in not only the conventional system but also a low-voltage one. Moreover, an operating method of the sort that conforms to specifications restrictive to both the relatively high operating voltage as used in the conventional system and the low-voltage system renders extendable a range of uses of such a semiconductor integrated circuit simple in construction.
    • 使得半导体集成电路的任何一个内部电路在具有预定允许范围的相对较高的工作电压下工作，并在具有预定允许范围的较低工作电压下工作。 工作电压由外部供电。 此外，构成半导体集成电路的内部电路的工作条件被分别设定为具有预定容许范围的较高工作电压和具有预定容许范围的较低工作电压。 使半导体集成电路在这些工作电压下选择性地工作。 由于内部电路以这两种工作电压工作，所以可以简化内部电路的布置，并且同时半导体集成电路不仅可以用于常规的系统，而且可以用于低电压。 此外，符合规范的规范的操作方法限于常规系统和低压系统中使用的相对较高的工作电压，使得这种半导体集成电路简单结构的使用范围可以扩展。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 15. 发明授权
      US5548146A Nonvolatile memory device having source and drain of memory cells integrally formed with data-source lines 失效
    • Nonvolatile memory device having source and drain of memory cells integrally formed with data-source lines
    • 具有与数据源线一体形成的存储单元的源极和漏极的非易失性存储器件
    • US5548146A
    • 1996-08-20
    • US470008
    • 1995-06-06
    • Kenichi Kuroda , Kazuyoshi Shiba , Akinori Matsuo
    • Kenichi Kuroda , Kazuyoshi Shiba , Akinori Matsuo
    • H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
    • G11C16/0491 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L29/7883
    • A semiconductor substrate of a first conductivity type has formed on its main surface a floating gate through a first gate insulating film and has further formed over the floating gate a control gate through a second gate insulating film. In one of a paired source and drain and across which there is provided the floating gate insulatedly above the main surface of the substrate, a semiconductor region of second conductivity type having a lower impurity concentration than that of the paired source and drain is formed in a portion of the substrate overlapping the floating gate. A nonvolatile memory device thus constructed has its writing operation carried out by extracting electrons from the floating gate to the other of the paired source and drain having a semiconductor region of the second conductivity type, having a higher impurity concentration, by an F-N tunneling of electrons flowing through the first gate insulating film and its erasing operation carried out by injecting from the paired source and drain or the semiconductor substrate into the floating gate by the F-N tunneling of electrons flowing through the first gate insulating film. Data lines or source lines can be shared between memory cells adjacent to each other in a word line direction so that the memory cells can be substantially small-sized. The writing operation and the erasing operation can be carried out by the tunnel current so that the corresponding, necessary high voltages can be generated by the internal circuits.
    • 第一导电类型的半导体衬底在其主表面上通过第一栅极绝缘膜形成浮栅，并且还通过第二栅极绝缘膜在浮栅上形成控制栅极。 在成对的源极和漏极中的一个中，在衬底的主表面上绝缘地设置浮置栅极，形成具有比成对的源极和漏极的杂质浓度低的第二导电类型的半导体区域 衬底的一部分与浮动栅极重叠。 如此构造的非易失性存储器件的写入操作是通过将电子从浮栅提取到具有具有较高杂质浓度的第二导电类型的半导体区域的成对源极和漏极中的另一个，通过电子的FN隧穿 流过第一栅极绝缘膜及其擦除操作，其通过由穿过第一栅极绝缘膜的电子的FN隧穿而从成对的源极和漏极或半导体衬底注入到浮置栅极中进行。 数据线或源极线可以在字线方向上彼此相邻的存储单元之间共享，使得存储器单元可以基本上小型化。 可以通过隧道电流进行写入操作和擦除操作，使得内部电路可以产生相应的必要的高电压。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 19. 发明授权
      US5747849A Nonvolatile memory device having buried data lines and floating gate electrode on buried data lines 失效
    • Nonvolatile memory device having buried data lines and floating gate electrode on buried data lines
    • 非易失性存储器件在掩埋数据线上具有埋置的数据线和浮栅电极
    • US5747849A
    • 1998-05-05
    • US669938
    • 1996-06-25
    • Kenichi Kuroda , Kazuyoshi Shiba , Akinori Matsuo
    • Kenichi Kuroda , Kazuyoshi Shiba , Akinori Matsuo
    • H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
    • G11C16/0491 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L29/7883
    • A semiconductor substrate of a first conductivity type has formed on its main surface a floating gate through a first gate insulating film and has further formed over the floating gate a control gate through a second gate insulating film. In one of a paired source and drain and across which there is provided the floating gate insulately above the main surface of the substrate, a semiconductor region of second conductivity type having a lower impurity concentration than that of the paired source and drain is formed in a portion of the substrate overlapping the floating gate. A nonvolatile memory device thus constructed has its writing operation carried out by extracting electrons from the floating gate to the other of the paired source and drain having a semiconductor region of the second conductivity type, having a higher impurity concentration, by an F-N tunneling of electrons flowing through the first gate insulating film and its erasing operation carried out by injecting from the paired source and drain or the semiconductor substrate into the floating gate by the F-N tunneling of electrons flowing through the first gate insulating film. Data lines or source lines can be shared between memory cells adjacent to each other in a word line direction so that the memory cells can be substantially small-sized. The writing operation and the erasing operation can be carried out by the tunnel current so that the corresponding necessary high voltages can be generated by the internal circuits.
    • 第一导电类型的半导体衬底在其主表面上通过第一栅极绝缘膜形成浮栅，并且还通过第二栅极绝缘膜在浮栅上形成控制栅极。 在成对的源极和漏极中的一个中，在衬底的主表面上绝缘地设置浮置栅极，具有比成对的源极和漏极的杂质浓度低的第二导电类型的半导体区域形成在 衬底的一部分与浮动栅极重叠。 如此构造的非易失性存储器件的写入操作是通过将电子从浮栅提取到具有具有较高杂质浓度的第二导电类型的半导体区域的成对源极和漏极中的另一个，通过电子的FN隧穿 流过第一栅极绝缘膜及其擦除操作，其通过由穿过第一栅极绝缘膜的电子的FN隧穿而从成对的源极和漏极或半导体衬底注入到浮置栅极中进行。 数据线或源极线可以在字线方向上彼此相邻的存储单元之间共享，使得存储器单元可以基本上小型化。 可以通过隧道电流进行写入操作和擦除操作，使得内部电路可以产生相应的必要的高电压。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 20. 发明授权
      US5444663A Semiconductor integrated circuit operable and programmable at multiple voltage levels 失效
    • Semiconductor integrated circuit operable and programmable at multiple voltage levels
    • 半导体集成电路在多个电压电平下可操作和可编程
    • US5444663A
    • 1995-08-22
    • US893802
    • 1992-06-04
    • Takeshi Furuno , Yasuhiro Nakamura , Akinori Matsuo
    • Takeshi Furuno , Yasuhiro Nakamura , Akinori Matsuo
    • G11C17/00 , G11C5/14 , G11C16/06 , G11C8/00
    • G11C5/143
    • Each internal circuit of a semiconductor integrated circuit operates at both a relatively high operating voltage having a predetermined allowable range and a relatively low operating voltage also having a predetermined allowable range. The operating voltage is externally supplied. Operating conditions of the semiconductor integrated circuit are individually set restrictive to the relatively high operating voltage having a predetermined allowable range and to the relatively low operating voltage having a predetermined allowable range. The semiconductor integrated circuit is operable selectively at these operating voltages. Since the internal circuits are operated at two operating voltages, an arrangement of internal circuits can be simplified while the semiconductor integrated circuit is concurrently usable in not only the conventional system but also a low-voltage one. Moreover, an operating method of the sort that conforms to specifications restrictive of both the relatively high operating voltage as used in the conventional system and the low-voltage system renders a simply constructed integrated circuit with an extendable a range of uses.
    • 半导体集成电路的每个内部电路在具有预定容许范围的相对较高的工作电压和也具有预定容许范围的较低工作电压的情况下工作。 外部提供工作电压。 半导体集成电路的工作条件被分别设定为具有预定容许范围的较高工作电压和具有预定容许范围的较低工作电压。 半导体集成电路可在这些工作电压下选择性地工作。 由于内部电路在两个工作电压下操作，所以可以简化内部电路的布置，而半导体集成电路不仅可以在常规系统中使用，而且可以用于低电压。 此外，符合限制常规系统中使用的相对高的工作电压的规格的操作方法和低电压系统使得简单构造的集成电路具有可扩展的使用范围。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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