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11. 发明申请

US20080303102A1 Strained Isolation Regions 有权
标题翻译：应变隔离区域
公开(公告)号：US20080303102A1
公开(公告)日：2008-12-11
申请号：US11759791
申请日：2007-06-07
申请人： Mong-Song Liang , Tze-Liang Lee , Kuo-Tai Huang , Chao-Cheng Chen , Hao-Ming Lien , Chih-Tang Peng
发明人： Mong-Song Liang , Tze-Liang Lee , Kuo-Tai Huang , Chao-Cheng Chen , Hao-Ming Lien , Chih-Tang Peng
IPC分类号： H01L29/78
CPC分类号： H01L29/1054 , H01L21/76224 , H01L29/7833 , H01L29/7843 , H01L29/7846
摘要： An isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.
摘要翻译：提供了具有局部应力源的隔离沟槽。根据本发明的实施例，在衬底中形成沟槽并且部分地填充有电介质材料。在一个实施例中，沟槽被填充有电介质层，并且执行平面化步骤以使其与衬底的表面平坦化。然后将电介质材料凹入到衬底的表面下方。在沟槽的凹陷部分中，电介质材料可以沿着侧壁保留，或者电介质材料可以沿侧壁去除。然后可以在凹陷部分内的电介质材料上形成拉伸或压缩的应力膜。应力膜也可以在晶体管或其它半导体结构上延伸。

12. 发明授权

US07851328B2 STI stress modulation with additional implantation and natural pad sin mask 有权
标题翻译： STI应力调制与附加植入和天然衬垫sin掩模
公开(公告)号：US07851328B2
公开(公告)日：2010-12-14
申请号：US12235329
申请日：2008-09-22
申请人： Ming-Han Liao , Tze-Liang Lee , Ling-Yen Yeh , Mong-Song Liang
发明人： Ming-Han Liao , Tze-Liang Lee , Ling-Yen Yeh , Mong-Song Liang
IPC分类号： H01L21/76
CPC分类号： H01L21/76237 , H01L21/823807 , H01L21/823878 , H01L29/7846
摘要： A method of manufacturing a semiconductor structure is provided. The method includes forming a hard mask pattern on a semiconductor substrate, wherein the hard mask pattern covers active regions; forming a trench in the semiconductor substrate within an opening defined by the hard mask pattern; filling the trench with a dielectric material, resulting in a trench isolation feature; performing an ion implantation to the trench isolation feature using the hard mask pattern to protect active regions of the semiconductor substrate; and removing the hard mask pattern after the performing of the ion implantation.
摘要翻译：提供一种制造半导体结构的方法。该方法包括在半导体衬底上形成硬掩模图案，其中硬掩模图案覆盖有源区; 在由所述硬掩模图案限定的开口内在所述半导体衬底中形成沟槽; 用电介质材料填充沟槽，导致沟槽隔离特征; 使用所述硬掩模图案对所述沟槽隔离特征进行离子注入以保护所述半导体衬底的有源区; 并且在执行离子注入之后去除硬掩模图案。

13. 发明授权

US07528028B2 Super anneal for process induced strain modulation 有权
标题翻译：过程诱导应变调制的超退火
公开(公告)号：US07528028B2
公开(公告)日：2009-05-05
申请号：US11199011
申请日：2005-08-08
申请人： Mong Song Liang , Chien-Hao Chen , Chun-Feng Nieh , Pang-Yen Tsai , Tze-Liang Lee , Shih-Chang Chen
发明人： Mong Song Liang , Chien-Hao Chen , Chun-Feng Nieh , Pang-Yen Tsai , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823412 , H01L21/7624 , H01L21/823468 , H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method for forming a semiconductor structure includes providing a substrate, forming a first device region on the substrate, forming a stressor layer overlying the first device region, and super annealing the stressor layer in the first device region, preferably by exposing the substrate to a high-energy radiance source, so that the stressor layer is super annealed for a substantially short duration. Preferably, the method further includes masking a second device region on the substrate while the first device region is super annealed. Alternatively, after the stressor layer in the first region is annealed, the stressor layer in the second device region is super annealed. A semiconductor structure formed using the method has different strains in the first and second device regions.
摘要翻译：一种用于形成半导体结构的方法包括：提供衬底，在衬底上形成第一器件区域，形成覆盖第一器件区域的应力层，以及对第一器件区域中的应力层进行超退火，优选通过将衬底暴露于高能量辐射源，使得应力层在超短时间内进行超退火。优选地，该方法还包括在第一器件区域被超退火时掩蔽衬底上的第二器件区域。或者，在第一区域中的应力层退火之后，第二器件区域中的应力层被超退火。使用该方法形成的半导体结构在第一和第二器件区域中具有不同的应变。

14. 发明授权

US08736016B2 Strained isolation regions 有权
标题翻译：应变隔离区
公开(公告)号：US08736016B2
公开(公告)日：2014-05-27
申请号：US11759791
申请日：2007-06-07
申请人： Mong-Song Liang , Tze-Liang Lee , Kuo-Tai Huang , Chao-Cheng Chen , Hao-Ming Lien , Chih-Tang Peng
发明人： Mong-Song Liang , Tze-Liang Lee , Kuo-Tai Huang , Chao-Cheng Chen , Hao-Ming Lien , Chih-Tang Peng
IPC分类号： H01L29/78
CPC分类号： H01L29/1054 , H01L21/76224 , H01L29/7833 , H01L29/7843 , H01L29/7846
摘要： An isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.
摘要翻译：提供了具有局部应力源的隔离沟槽。根据本发明的实施例，在衬底中形成沟槽并且部分地填充有电介质材料。在一个实施例中，沟槽被填充有电介质层，并且执行平面化步骤以使其与衬底的表面平坦化。然后将电介质材料凹入到衬底的表面下方。在沟槽的凹陷部分中，电介质材料可以沿着侧壁保留，或者电介质材料可以沿侧壁去除。然后可以在凹陷部分内的电介质材料上形成拉伸或压缩的应力膜。应力膜也可以在晶体管或其它半导体结构上延伸。

15. 发明授权

US09054130B2 Bottle-neck recess in a semiconductor device 有权
标题翻译：半导体器件中的瓶颈凹槽
公开(公告)号：US09054130B2
公开(公告)日：2015-06-09
申请号：US12841763
申请日：2010-07-22
申请人： Eric Peng , Chao-Cheng Chen , Ming-Hua Yu , Ying Hao Hsieh , Tze-Liang Lee , Chii-Horng Li , Syun-Ming Jang , Shih-Hao Lo
发明人： Eric Peng , Chao-Cheng Chen , Ming-Hua Yu , Ying Hao Hsieh , Tze-Liang Lee , Chii-Horng Li , Syun-Ming Jang , Shih-Hao Lo
IPC分类号： H01L21/302 , H01L29/66 , H01L21/306 , H01L21/3065 , H01L29/165
CPC分类号： H01L29/7848 , H01L21/30608 , H01L21/3065 , H01L29/165 , H01L29/66636
摘要： The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas. An embodiment may include performing an oxidation process to the recess region in the silicon substrate by adding oxygen gas to form silicon oxide on a portion of the recess region in the silicon substrate. As such, these processes form polymer protection to help form the bottle-neck shaped recess.
摘要翻译：本公开提供了一种制造半导体器件的方法，其包括提供硅衬底，在硅衬底上形成栅极堆叠，对衬底执行偏置的干蚀刻工艺以去除硅衬底的一部分，从而形成凹陷区域在硅衬底中，对硅衬底中的凹陷区域进行非偏置蚀刻工艺，从而在硅衬底中形成瓶颈形凹部区域，并且在瓶颈形凹部区域中生长半导体材料在硅衬底中。一个实施例可以包括偏置的干蚀刻工艺，包括加入HeO2气体和HBr气体。实施例可以包括执行包括N 2气体的第一偏压干法蚀刻工艺，并执行不包括N 2气体的第二偏压干式蚀刻工艺。一个实施例可以包括通过在硅衬底中的一部分凹陷区域上添加氧气以形成氧化硅，来对硅衬底中的凹陷区域进行氧化处理。因此，这些方法形成聚合物保护以帮助形成瓶颈形凹部。

16. 发明授权

US08530316B2 Method for fabricating a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08530316B2
公开(公告)日：2013-09-10
申请号：US13736453
申请日：2013-01-08
申请人： Yu-Hung Cheng , Jhi-Cherng Lu , Ming-Hua Yu , Chii-Horng Li , Tze-Liang Lee
发明人： Yu-Hung Cheng , Jhi-Cherng Lu , Ming-Hua Yu , Chii-Horng Li , Tze-Liang Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/20 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02636 , H01L21/3065 , H01L21/823412 , H01L21/823425 , H01L21/823807 , H01L21/823814 , H01L29/66477 , H01L29/7848
摘要： A method for fabricating a semiconductor device, the method including growing a first semiconductor structure comprising a first semiconductor material on a surface of a substrate, wherein growing the first semiconductor structure includes forming a semiconductor particle comprising the first semiconductor material on a second semiconductor structure of the semiconductor device. The method further includes forming a protection layer of a second semiconductor material on the first semiconductor structure, wherein forming the protection layer includes forming the protection layer on the semiconductor particle. The method further includes removing a portion of the protection layer, wherein removing the portion of the protection layer includes fully removing the protection layer on the semiconductor particle and the semiconductor particle.
摘要翻译：一种制造半导体器件的方法，所述方法包括在衬底的表面上生长包括第一半导体材料的第一半导体结构，其中生长第一半导体结构包括在第二半导体结构的第二半导体结构上形成包含第一半导体材料的半导体粒子半导体器件。该方法还包括在第一半导体结构上形成第二半导体材料的保护层，其中形成保护层包括在半导体颗粒上形成保护层。该方法还包括去除保护层的一部分，其中去除保护层的部分包括完全去除半导体颗粒和半导体颗粒上的保护层。

17. 发明申请

US20100289086A1 Source/Drain Strained Layers 有权
标题翻译：源/排水层
公开(公告)号：US20100289086A1
公开(公告)日：2010-11-18
申请号：US12844896
申请日：2010-07-28
申请人： Ming-Hua Yu , Ling-Yen Yeh , Tze-Liang Lee
发明人： Ming-Hua Yu , Ling-Yen Yeh , Tze-Liang Lee
IPC分类号： H01L27/092
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66628 , H01L29/66636
摘要： A semiconductor device and method of manufacture thereof wherein a PMOS source/drain region of a transistor within the substrate includes a first strained layer in the PMOS source/drain region and a first capping layer in contact with the first strained layer. Further, the semiconductor device and method provide for an NMOS source/drain region of a transistor within the substrate including a second strained layer in the NMOS source/drain region and a second capping layer in contact with the second strained layer.
摘要翻译：一种半导体器件及其制造方法，其中所述衬底内的晶体管的PMOS源极/漏极区域包括所述PMOS源极/漏极区域中的第一应变层和与所述第一应变层接触的第一覆盖层。此外，半导体器件和方法提供了衬底内的晶体管的NMOS源极/漏极区域，其包括NMOS源极/漏极区域中的第二应变层和与第二应变层接触的第二覆盖层。

18. 发明申请

US20070298593A1 Epitaxy silicon on insulator (ESOI) 有权
标题翻译：外延绝缘体硅（ESOI）
公开(公告)号：US20070298593A1
公开(公告)日：2007-12-27
申请号：US11521667
申请日：2006-09-15
申请人： Ming-Hua Yu , Tze-Liang Lee , Pang-Yen Tsai
发明人： Ming-Hua Yu , Tze-Liang Lee , Pang-Yen Tsai
IPC分类号： H01L21/20 , H01L21/84 , H01L21/76
CPC分类号： H01L29/0649 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/517 , H01L29/6659 , H01L29/7843 , H01L29/7846
摘要： Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a second dielectric layer on the second epitaxial layer. A semiconductor fabrication method comprises forming a dielectric layer over a substrate and surrounding a device fabrication region in the substrate with an isolation trench extending through the dielectric layer. The method also includes filling the isolation trench with a first epitaxial layer and forming a second epitaxial layer over the device fabrication region and over the first epitaxial layer. Then a portion of the first epitaxial layer is replaced with an isolation dielectric, and then a device such as a transistor is formed second epitaxial layer within the device fabrication region.
摘要翻译：提供了SOI衬底中具有STI区域的半导体器件的方法和结构。半导体结构包括在衬底上形成的SOI外延岛。该结构还包括围绕SOI岛的STI结构。 STI结构包括在衬底上的第二外延层和在第二外延层上的第二电介质层。一种半导体制造方法包括在衬底上形成介电层并围绕延伸穿过介电层的隔离沟槽围绕衬底中的器件制造区域。该方法还包括用第一外延层填充隔离沟槽，并在器件制造区域上方和第一外延层上形成第二外延层。然后用绝缘电介质代替第一外延层的一部分，然后在器件制造区域内形成诸如晶体管的器件的第二外延层。

19. 发明授权

US08927374B2 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08927374B2
公开(公告)日：2015-01-06
申请号：US13252346
申请日：2011-10-04
申请人： Lilly Su , Pang-Yen Tsai , Tze-Liang Lee , Chii-Horng Li , Yen-Ru Lee , Ming-Hua Yu
发明人： Lilly Su , Pang-Yen Tsai , Tze-Liang Lee , Chii-Horng Li , Yen-Ru Lee , Ming-Hua Yu
IPC分类号： H01L21/336 , H01L29/04 , H01L21/8234 , H01L21/8238 , H01L29/66 , H01L29/78 , H01L29/08
CPC分类号： H01L29/7848 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/0617 , H01L29/045 , H01L29/0653 , H01L29/0843 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of the substrate to enhance carrier mobility and upgrade the device performance. The improved formation method is achieved by providing a treatment to redistribute at least a portion of the corner in the cavity.
摘要翻译：公开了一种制造半导体器件的方法。应变材料形成在衬底的空腔中并与衬底中的隔离结构相邻。应变材料在基底表面上方有一角。所公开的方法提供了一种用于在隔离结构附近形成应变材料的改进方法，其中在衬底的空腔中增加部分以增强载体移动性并提高器件性能。改进的形成方法通过提供一种处理来重新分布空腔中角部的至少一部分来实现。

20. 发明授权

US08835267B2 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08835267B2
公开(公告)日：2014-09-16
申请号：US13248319
申请日：2011-09-29
申请人： Yen-Ru Lee , Ming-Hua Yu , Tze-Liang Lee , Chii-Horng Li , Pang-Yen Tsai , Lilly Su , Yi-Hung Lin , Yu-Hung Cheng
发明人： Yen-Ru Lee , Ming-Hua Yu , Tze-Liang Lee , Chii-Horng Li , Pang-Yen Tsai , Lilly Su , Yi-Hung Lin , Yu-Hung Cheng
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L29/78 , H01L29/66
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02661 , H01L21/30604 , H01L21/30608 , H01L21/3065 , H01L21/3083 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/045 , H01L29/0653 , H01L29/0847 , H01L29/66545 , H01L29/66636 , H01L29/7845 , H01L29/7846
摘要： A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of a substrate to enhance carrier mobility and upgrade the device performance. In an embodiment, the improved formation method is achieved using an etching process to redistribute the strained material by removing at least a portion of the corner to be located in the cavity.
摘要翻译：公开了一种制造半导体器件的方法。应变材料形成在衬底的空腔中并与衬底中的隔离结构相邻。应变材料在基底表面上方有一角。所公开的方法提供了一种用于形成邻近隔离结构的应变材料的改进方法，其中衬底的腔中具有增加的部分，以增强载体移动性并提高器件性能。在一个实施例中，改进的形成方法是通过使用蚀刻工艺来实现的，该蚀刻工艺通过去除位于空腔中的角部的至少一部分来重新分布应变材料。

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