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11. 发明申请

US20100018944A1 PATTERNING METHOD 审中-公开
标题翻译：绘图方法
公开(公告)号：US20100018944A1
公开(公告)日：2010-01-28
申请号：US12179879
申请日：2008-07-25
申请人： Yu-Tsung Lai , Shih-Chang Chang , Chieh-Ju Wang , Jyh-Cherng Yau , Jiunn-Hsiung Liao
发明人： Yu-Tsung Lai , Shih-Chang Chang , Chieh-Ju Wang , Jyh-Cherng Yau , Jiunn-Hsiung Liao
IPC分类号： H01B13/00
CPC分类号： H01L21/31144 , H01L21/0273 , H01L21/31116 , H01L21/31138
摘要： A patterning method is provided. A patterned photoresist layer is formed on a bottom anti-reflective coating (BARC), having therein an opening exposing a portion of the BARC. The patterned photoresist layer is treated with a first plasma-generating gas including a fluorocarbon species to form a polymer layer on the surface of the PR layer and the sidewall of the opening. The patterned photoresist layer is used as a mask to etch the BARC with a second plasma-generating gas, which includes Ar and H2 but no fluorocarbon species or oxygen-containing species, to remove the exposed portion of the BARC.
摘要翻译：提供了图案化方法。在底部抗反射涂层（BARC）上形成图案化的光致抗蚀剂层，其中具有露出BARC的一部分的开口。图案化的光致抗蚀剂层用包括碳氟化合物种的第一等离子体产生气体处理，以在PR层的表面和开口的侧壁上形成聚合物层。图案化的光致抗蚀剂层用作掩模以具有第二等离子体产生气体（其包括Ar和H 2，但不含碳氟物质或含氧物质）来蚀刻BARC以去除BARC的暴露部分。

12. 发明申请

US20090142931A1 Cleaning method following opening etch 有权
标题翻译：打开蚀刻后的清洁方法
公开(公告)号：US20090142931A1
公开(公告)日：2009-06-04
申请号：US11946875
申请日：2007-11-29
申请人： Chieh-Ju Wang , Jyh-Cherng Yau , Yu-Tsung Lai , Jiunn-Hsiung Liao
发明人： Chieh-Ju Wang , Jyh-Cherng Yau , Yu-Tsung Lai , Jiunn-Hsiung Liao
IPC分类号： H01L21/461 , C23F1/12
CPC分类号： H01L21/02063 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L21/76814
摘要： A cleaning method following an opening etching is provided. First, a semiconductor substrate having a dielectric layer is provided. The hard mask layer includes at least a metal layer. The opening etch is then carried out to form at least an opening in the dielectric layer. A nitrogen (N2) treatment process is performed to clean polymer residues having carbon-fluorine (C—F) bonds remained in the opening. Finally, a wet cleaning process is performed.
摘要翻译：提供了开口蚀刻后的清洁方法。首先，提供具有电介质层的半导体基板。硬掩模层至少包括金属层。然后进行开口蚀刻以形成电介质层中的至少一个开口。进行氮（N2）处理工艺以清洁残留在开口中的具有碳 - 氟（C-F）键的聚合物残基。最后，进行湿式清洗处理。

13. 发明授权

US08080877B2 Damascene interconnection structure and dual damascene process thereof 有权
标题翻译：大马士革互连结构及其双镶嵌工艺
公开(公告)号：US08080877B2
公开(公告)日：2011-12-20
申请号：US12821136
申请日：2010-06-23
申请人： Chun-Jen Huang , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
发明人： Chun-Jen Huang , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76811
摘要： A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.
摘要翻译：公开了一种双镶嵌工艺。提供了具有基底电介质层，嵌入基底电介质层中的下部布线层和覆盖下部布线层的盖层的基板。介电层沉积在盖层上。氧化硅层沉积在电介质层上。在氧化硅层上形成金属硬掩模。将沟槽开口蚀刻到金属硬掩模中。部分通孔特征被蚀刻到沟槽开口内的电介质层中。沟槽开口和部分通孔特征被蚀刻转移到电介质层中，从而形成暴露盖层的一部分的双镶嵌开口。执行衬垫去除步骤以通过使用CF4 / NF3等离子体从双镶嵌开口选择性地去除暴露的盖层。

14. 发明申请

US20100258941A1 DAMASCENE INTERCONNECTION STRUCTURE AND DUAL DAMASCENE PROCESS THEREOF 有权
标题翻译：大连互连结构及其双重破坏过程
公开(公告)号：US20100258941A1
公开(公告)日：2010-10-14
申请号：US12821136
申请日：2010-06-23
申请人： Chun-Jen Huang , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
发明人： Chun-Jen Huang , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
IPC分类号： H01L23/532
CPC分类号： H01L21/76811
摘要： A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.
摘要翻译：公开了一种双镶嵌工艺。提供了具有基底电介质层，嵌入基底电介质层中的下部布线层和覆盖下部布线层的盖层的基板。介电层沉积在盖层上。氧化硅层沉积在电介质层上。在氧化硅层上形成金属硬掩模。将沟槽开口蚀刻到金属硬掩模中。部分通孔特征被蚀刻到沟槽开口内的电介质层中。沟槽开口和部分通孔特征被蚀刻转移到电介质层中，从而形成暴露盖层的一部分的双镶嵌开口。执行衬垫去除步骤以通过使用CF4 / NF3等离子体从双镶嵌开口选择性地去除暴露的盖层。

15. 发明授权

US08323877B2 Patterning method and method for fabricating dual damascene opening 有权
标题翻译：用于制作双镶嵌开口的图案化方法和方法
公开(公告)号：US08323877B2
公开(公告)日：2012-12-04
申请号：US12947139
申请日：2010-11-16
申请人： Ming-Da Hsieh , Yu-Tsung Lai , Jiunn-Hsiung Liao
发明人： Ming-Da Hsieh , Yu-Tsung Lai , Jiunn-Hsiung Liao
IPC分类号： G03F7/26
CPC分类号： H01L21/76811 , G03F7/094 , H01L21/31138 , H01L21/31144 , H01L21/76802
摘要： A patterning method and a method for fabricating a dual damascene opening are described, wherein the patterning method includes following steps. An organic layer, a silicon-containing mask layer and a patterned photoresist layer are formed on a material layer in sequence. The silicon-containing mask layer is removed using the patterned photoresist layer as a mask. A reactive gas is used for conducting an etching step so as to remove the organic layer with the silicon-containing mask layer as a mask, wherein the reactive gas contains no oxygen species. The material layer is removed using the organic layer as a mask, so that an opening is formed in the material layer. The organic layer is then removed.
摘要翻译：描述了用于制造双镶嵌开口的图案化方法和方法，其中图案化方法包括以下步骤。在材料层上依次形成有机层，含硅掩模层和图案化的光致抗蚀剂层。使用图案化的光致抗蚀剂层作为掩模去除含硅掩模层。使用反应性气体进行蚀刻步骤，以便以含硅掩模层作为掩模去除有机层，其中反应气体不含氧物质。使用有机层作为掩模去除材料层，从而在材料层中形成开口。然后除去有机层。

16. 发明申请

US20120122035A1 PATTERNING METHOD AND METHOD FOR FABRICATING DUAL DAMASCENE OPENING 有权
标题翻译：用于制备双重开花的方法和方法
公开(公告)号：US20120122035A1
公开(公告)日：2012-05-17
申请号：US12947139
申请日：2010-11-16
申请人： MING-DA HSIEH , Yu-Tsung Lai , Jiunn-Hsiung Liao
发明人： MING-DA HSIEH , Yu-Tsung Lai , Jiunn-Hsiung Liao
IPC分类号： G03F7/20
CPC分类号： H01L21/76811 , G03F7/094 , H01L21/31138 , H01L21/31144 , H01L21/76802
摘要： A patterning method and a method for fabricating a dual damascene opening are described, wherein the patterning method includes following steps. An organic layer, a silicon-containing mask layer and a patterned photoresist layer are formed on a material layer in sequence. The silicon-containing mask layer is removed using the patterned photoresist layer as a mask. A reactive gas is used for conducting an etching step so as to remove the organic layer with the silicon-containing mask layer as a mask, wherein the reactive gas contains no oxygen species. The material layer is removed using the organic layer as a mask, so that an opening is formed in the material layer. The organic layer is then removed.
摘要翻译：描述了用于制造双镶嵌开口的图案化方法和方法，其中图案化方法包括以下步骤。在材料层上依次形成有机层，含硅掩模层和图案化的光致抗蚀剂层。使用图案化的光致抗蚀剂层作为掩模去除含硅掩模层。使用反应性气体进行蚀刻步骤，以便以含硅掩模层作为掩模去除有机层，其中反应气体不含氧物质。使用有机层作为掩模去除材料层，从而在材料层中形成开口。然后除去有机层。

17. 发明申请

US20120289043A1 METHOD FOR FORMING DAMASCENE TRENCH STRUCTURE AND APPLICATIONS THEREOF 审中-公开
标题翻译：用于形成大气结晶结构的方法及其应用
公开(公告)号：US20120289043A1
公开(公告)日：2012-11-15
申请号：US13105987
申请日：2011-05-12
申请人： Ming-Da HSIEH , Yu-Tsung Lai , Jiunn-Hsiung Liao
发明人： Ming-Da HSIEH , Yu-Tsung Lai , Jiunn-Hsiung Liao
IPC分类号： H01L21/768
CPC分类号： H01L21/31116 , H01L21/31144 , H01L21/32136 , H01L21/76804 , H01L21/76811
摘要： A method for fabricating a damascene trench structure, wherein the method comprises steps as follows: A semiconductor structure having an inner layer dielectric (ILD) and a patterned hard mask stacked in sequence is firstly provided, in which a trench extends from the patterned hard mask downwards into the ILD. Subsequently, the patterned hard mask is etched in an atmosphere essentially consisting of nitrogen (N2) and carbon-fluoride compositions (CxFy).
摘要翻译：一种用于制造镶嵌沟槽结构的方法，其中该方法包括以下步骤：首先提供具有内层电介质（ILD）和依次层叠的图案化硬掩模的半导体结构，其中沟槽从图案化的硬掩模向下进入ILD。随后，将图案化的硬掩模在基本上由氮（N 2）和氟化碳组合物（C x F y）组成的气氛中进行蚀刻。

18. 发明授权

US08592304B2 Method for filling metal 有权
标题翻译：填充金属的方法
公开(公告)号：US08592304B2
公开(公告)日：2013-11-26
申请号：US12757017
申请日：2010-04-08
申请人： Chang-Hsiao Lee , Yu-Tsung Lai , Jiunn-Hsiung Liao
发明人： Chang-Hsiao Lee , Yu-Tsung Lai , Jiunn-Hsiung Liao
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76804 , H01L21/02063 , H01L21/32139 , H01L21/76814
摘要： A method for filling a metal is disclosed. First, a substrate is provided. The substrate includes a metal material layer, a dielectric layer covering the metal material layer and a hard mask layer covering the dielectric layer. The hard mask layer has at least one opening to expose the underlying dielectric layer. Second, a dry etching step is performed to etch the dielectric layer through the opening to remove part of the dielectric layer to expose the metal material layer and to form a recess and leave some residues in the recess. Then a cleaning step is performed to remove the residues and to selectively remove part of the hard mask to substantially enlarge the opening. Later, a metal fills the recess through the enlarged opening.
摘要翻译：公开了一种填充金属的方法。首先，提供基板。基板包括金属材料层，覆盖金属材料层的电介质层和覆盖电介质层的硬掩模层。硬掩模层具有至少一个开口以暴露下面的介电层。第二，进行干蚀刻步骤以通过开口蚀刻介电层以去除介电层的一部分以暴露金属材料层并形成凹槽并在凹部中留下一些残留物。然后执行清洁步骤以去除残留物并选择性地去除硬掩模的一部分以基本上扩大开口。之后，金属通过扩大的开口填充凹槽。

19. 发明授权

US08298935B2 Dual damascene process 有权
标题翻译：双镶嵌工艺
公开(公告)号：US08298935B2
公开(公告)日：2012-10-30
申请号：US12952179
申请日：2010-11-22
申请人： Shin-Chi Chen , Yu-Tsung Lai , Jiunn-Hsiung Liao , Guang-Yaw Hwang
发明人： Shin-Chi Chen , Yu-Tsung Lai , Jiunn-Hsiung Liao , Guang-Yaw Hwang
IPC分类号： H01L21/4763
CPC分类号： H01L21/7681 , H01L21/31144 , H01L21/76811
摘要： A dual damascene process is disclosed. The process includes the steps of: forming a dielectric layer on a substrate; forming a first patterned mask on the dielectric layer, wherein the first patterned mask comprises an opening; forming a material layer on the dielectric layer and covering the first patterned mask; forming a second patterned mask on the dielectric layer, wherein the second patterned mask comprises a first aperture; forming a second aperture in the second patterned mask, wherein the second aperture and the first aperture comprise a gap therebetween; and utilizing the second patterned mask as etching mask for partially removing the material layer and the dielectric layer through the first aperture and the second aperture.
摘要翻译：公开了一种双镶嵌工艺。该方法包括以下步骤：在基底上形成电介质层; 在所述电介质层上形成第一图案化掩模，其中所述第一图案化掩模包括开口; 在所述电介质层上形成材料层并覆盖所述第一图案化掩模; 在所述电介质层上形成第二图案化掩模，其中所述第二图案化掩模包括第一孔; 在所述第二图案化掩模中形成第二孔，其中所述第二孔和所述第一孔包括它们之间的间隙; 并且利用第二图案化掩模作为蚀刻掩模，用于通过第一孔和第二孔部分去除材料层和介电层。

20. 发明授权

US08277674B2 Method of removing post-etch residues 有权
标题翻译：去除蚀刻后残留物的方法
公开(公告)号：US08277674B2
公开(公告)日：2012-10-02
申请号：US12637762
申请日：2009-12-15
申请人： Chang-Hsiao Lee , Yu-Tsung Lai , Jiunn-Hsiung Liao
发明人： Chang-Hsiao Lee , Yu-Tsung Lai , Jiunn-Hsiung Liao
IPC分类号： C23F1/00
CPC分类号： H01L21/31144 , H01L21/02071 , H01L21/32138
摘要： A method of removing post-etch residues is provided. First, a substrate is provided. An isolation layer covers the substrate and a conductive layer is embedded in the isolation layer. A dielectric layer and a hard mask cover the isolation layer. Then, an etching process is performed, and a patterned hard mask is formed by etching the hard mask by ions or atoms. After that, a charge-removing process is performed by using a conductive solution to cleaning the patterned hard mask and the dielectric layer so as to remove the charges accumulated on the patterned hard mask and the dielectric layer during the etch process. Finally, the post-etch residues on the patterned hard mask and the dielectric layer is removed.
摘要翻译：提供了去除蚀刻后残留物的方法。首先，提供基板。隔离层覆盖基板，并且导电层嵌入在隔离层中。介电层和硬掩模覆盖隔离层。然后，进行蚀刻处理，通过用离子或原子蚀刻硬掩模来形成图案化的硬掩模。之后，通过使用导电溶液来清洁图案化的硬掩模和电介质层，从而去除在刻蚀过程中累积在图案化的硬掩模和电介质层上的电荷，进行电荷去除处理。最后，去除图案化硬掩模和电介质层上的蚀刻后残留物。

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