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11. 发明申请

US20060134437A1 Protective layer, composite for forming the protective layer, method of forming the protective layer, and plasma display panel including the protective layer 有权
标题翻译：保护层，用于形成保护层的复合材料，形成保护层的方法和包括保护层的等离子体显示面板
公开(公告)号：US20060134437A1
公开(公告)日：2006-06-22
申请号：US11284621
申请日：2005-11-22
申请人： Min-Suk Lee , Jong-Seo Choi , Suk-Ki Kim , Yuri Matulevich , Jae-Hyuk Kim , Soon-Sung Suh
发明人： Min-Suk Lee , Jong-Seo Choi , Suk-Ki Kim , Yuri Matulevich , Jae-Hyuk Kim , Soon-Sung Suh
IPC分类号： C04B35/50 , C04B35/04
CPC分类号： C03C17/3642 , C03C17/36 , C03C17/3657 , C03C17/3671 , C03C2217/40 , H01J11/12 , H01J11/40
摘要： Provided are a protective layer made of magnesium oxide containing at least one rare earth element selected from the group consisting of the rare earth elements, in which the content of the at least one rare earth element is from about 5.0×10−5 to about 6.0×10−4 per 1 part by weight of the magnesium oxide, a composite for forming the protective layer, a method of forming the protective layer, and a plasma display panel including the protective layer. The protective layer can reduce a discharge delay time and the temperature dependency of the discharge delay time, and thus, is suitable for single scan and an increase in Xe content.
摘要翻译：提供一种由氧化镁制成的保护层，其含有选自由稀土元素组成的组中的至少一种稀土元素，其中至少一种稀土元素的含量为约5.0×10 -5〜 / SUP>至约6.0×10 -4的氧化镁，用于形成保护层的复合材料，形成保护层的方法和包括保护层的等离子体显示面板层。保护层可以减少放电延迟时间和放电延迟时间的温度依赖性，因此适用于单次扫描和Xe含量的增加。

12. 发明申请

US20060038495A1 Protective layer for plasma display panel and method for forming the same 审中-公开
标题翻译：等离子体显示面板用保护层及其形成方法
公开(公告)号：US20060038495A1
公开(公告)日：2006-02-23
申请号：US11208084
申请日：2005-08-19
申请人： Min-Suk Lee , Jong-Seo Choi , Suk-Ki Kim , Jae-Hyuk Kim , Soon-Sung Suh
发明人： Min-Suk Lee , Jong-Seo Choi , Suk-Ki Kim , Jae-Hyuk Kim , Soon-Sung Suh
IPC分类号： H01J17/49
CPC分类号： H01J11/12 , H01J11/40
摘要： Herein is provided a protective layer for a plasma display panel and a method of forming the protective layer. The protective layer is formed on a substrate of the plasma display panel which includes sustain electrodes. Grain columns having directionality are formed in the texture of the protective layer. Because the direction of the grain columns can be controlled, the general orientation of the voids is known, and an electric field can be applied for discharge in a direction where the number of voids is smallest. As a result, the etching rate of the protective layer can be reduced, thereby increasing the lifetime of the protective layer. In addition, since discharge ions are less likely to impact the protective layer rapid emission of secondary electrons and reduced discharge delay time is realized. It is therefore possible to shorten the discharge delay time and to improve the breakdown voltage of discharge.
摘要翻译：本发明提供了一种用于等离子体显示面板的保护层和形成保护层的方法。保护层形成在包括维持电极的等离子体显示面板的基板上。在保护层的纹理中形成具有方向性的晶粒。因为可以控制颗粒柱的方向，所以空隙的一般取向是已知的，并且可以在空隙数最小的方向上施加电场以进行放电。结果，可以降低保护层的蚀刻速率，从而增加保护层的寿命。此外，由于放电离子不太可能影响保护层，因此实现了二次电子的快速发射和放电延迟时间的缩短。因此可以缩短放电延迟时间并提高放电的击穿电压。

13. 发明授权

US07713639B2 Protective layer, composite for forming the protective layer, method of forming the protective layer, and plasma display panel including the protective layer 有权
标题翻译：保护层，用于形成保护层的复合材料，形成保护层的方法和包括保护层的等离子体显示面板
公开(公告)号：US07713639B2
公开(公告)日：2010-05-11
申请号：US11284621
申请日：2005-11-22
申请人： Min-Suk Lee , Jong-Seo Choi , Suk-Ki Kim , Yuri Matulevich , Jae-Hyuk Kim , Soon-Sung Suh
发明人： Min-Suk Lee , Jong-Seo Choi , Suk-Ki Kim , Yuri Matulevich , Jae-Hyuk Kim , Soon-Sung Suh
IPC分类号： B32B9/00
CPC分类号： C03C17/3642 , C03C17/36 , C03C17/3657 , C03C17/3671 , C03C2217/40 , H01J11/12 , H01J11/40
摘要： Provided are a protective layer made of magnesium oxide containing at least one rare earth element selected from the group consisting of the rare earth elements, in which the content of the at least one rare earth element is from about 5.0×10−5 to about 6.0×10−4 per 1 part by weight of the magnesium oxide, a composite for forming the protective layer, a method of forming the protective layer, and a plasma display panel including the protective layer. The protective layer can reduce a discharge delay time and the temperature dependency of the discharge delay time, and thus, is suitable for single scan and an increase in Xe content.
摘要翻译：提供一种由氧化镁制成的保护层，其含有至少一种选自稀土元素的稀土元素，其中至少一种稀土元素的含量为约5.0×10 -5至约6.0 ×10-4 / 1重量份的氧化镁，用于形成保护层的复合体，形成保护层的方法和包括该保护层的等离子体显示面板。保护层可以减少放电延迟时间和放电延迟时间的温度依赖性，因此适用于单次扫描和Xe含量的增加。

14. 发明申请

US20050288169A1 Protective layer of gas discharge display device and method of forming the same 审中-公开
标题翻译：气体放电显示装置的保护层及其形成方法
公开(公告)号：US20050288169A1
公开(公告)日：2005-12-29
申请号：US11165449
申请日：2005-06-23
申请人： Min-Suk Lee , Jong-Seo Choi , Min-Ho Oh , Jae-Hyuk Kim , Soon-Sung Suh
发明人： Min-Suk Lee , Jong-Seo Choi , Min-Ho Oh , Jae-Hyuk Kim , Soon-Sung Suh
IPC分类号： H01J17/49 , B05D5/12 , C04B35/043 , H01B3/10 , H01J9/02 , H01J11/22 , H01J11/24 , H01J11/34 , H01J11/40
CPC分类号： C04B35/043 , C04B2235/3203 , C04B2235/3287 , C04B2235/72 , H01J11/12 , H01J11/40
摘要： Provided is a protective layer formed using at least one selected from the group consisting of a magnesium oxide and a magnesium salt and at least one selected from the group consisting of a lithium salt, a lithium oxide, a germanium oxide, and a germanium element. Provided is also a composition for forming a protective layer. When the composition is used for a protective layer of a gas discharge display device, an electrode or a dielectric can be protected from plasma ions generated by discharge of a mixed gas of Ne+Xe or He+Ne+Xe, a lower discharge voltage and a shorter discharge lag time can be obtained.
摘要翻译：提供了使用选自氧化镁和镁盐中的至少一种和选自锂盐，氧化锂，氧化锗和锗元素中的至少一种形成的保护层。还提供了形成保护层的组合物。当组合物用于气体放电显示装置的保护层时，可以保护电极或电介质免受由Ne + Xe或He + Ne + Xe的混合气体排放而产生的等离子体离子，放电电压较低，可以获得较短的放电滞后时间。

15. 发明申请

US20070202691A1 Method for fabricating a semiconductor device with self-aligned contact 有权
标题翻译：用于制造具有自对准接触的半导体器件的方法
公开(公告)号：US20070202691A1
公开(公告)日：2007-08-30
申请号：US11646473
申请日：2006-12-28
申请人： Min-Suk Lee , Jae-Young Lee
发明人： Min-Suk Lee , Jae-Young Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897
摘要： A method for fabricating a semiconductor device includes forming electrode patterns over a substrate, wherein the electrode patterns include a hard mask, forming a passivation layer on the electrode patterns, forming an insulation layer on the passivation layer, filling a space between the electrode patterns, planarizing the insulation layer until shoulder portions of the hard mask are planarized, forming a mask pattern on a resultant structure, and etching a portion of the insulation layer to form a contact hole.
摘要翻译：一种用于制造半导体器件的方法包括在衬底上形成电极图案，其中电极图案包括硬掩模，在电极图案上形成钝化层，在钝化层上形成绝缘层，填充电极图案之间的空间，平面化绝缘层，直到硬掩模的肩部平坦化，在所得结构上形成掩模图案，并蚀刻绝缘层的一部分以形成接触孔。

16. 发明授权

US07196004B2 Method and fabricating semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07196004B2
公开(公告)日：2007-03-27
申请号：US10924720
申请日：2004-08-23
申请人： Min-Suk Lee , Sung-Kwon Lee
发明人： Min-Suk Lee , Sung-Kwon Lee
IPC分类号： H01L21/4763 , H01L21/425 , H01L21/302 , H01L21/461
CPC分类号： H01L21/76897
摘要： A method for fabricating a semiconductor device is capable of preventing a hard mask layer of a conductive structure from being damaged during a self-aligned contact etching process. The method includes the steps of: forming a plurality of conductive structures including a conductive layer and a hard mask layer on a substrate; sequentially forming a first nitride layer, an oxide layer, a second nitride layer, and an etch stop layer on the plurality of conductive structures; forming an inter-layer insulation layer on the etch stop layer; and performing a self-aligned contact (SAC) etching process selectively etching the inter-layer insulation layer, the etch stop layer, the second nitride layer and the oxide layer until the SAC etching process is stopped at the first nitride layer to thereby form a contact hole exposing the first nitride layer.
摘要翻译：一种制造半导体器件的方法能够防止导电结构的硬掩模层在自对准接触蚀刻工艺期间被损坏。该方法包括以下步骤：在衬底上形成包括导电层和硬掩模层的多个导电结构; 在所述多个导电结构上依次形成第一氮化物层，氧化物层，第二氮化物层和蚀刻停止层; 在所述蚀刻停止层上形成层间绝缘层; 以及执行自对准接触（SAC）蚀刻工艺，选择性地蚀刻层间绝缘层，蚀刻停止层，第二氮化物层和氧化物层，直到在第一氮化物层处停止SAC蚀刻工艺，从而形成露出第一氮化物层的接触孔。

17. 发明申请

US20070015356A1 Method for forming contact hole in semiconductor device 审中-公开
标题翻译：在半导体器件中形成接触孔的方法
公开(公告)号：US20070015356A1
公开(公告)日：2007-01-18
申请号：US11361525
申请日：2006-02-24
申请人： Min-Suk Lee , Sung-Kwon Lee
发明人： Min-Suk Lee , Sung-Kwon Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L2221/1057
摘要： A method for forming a contact hole in a semiconductor device is provided. A method for forming a contact hole in a semiconductor device includes: forming an insulation layer over a bottom structure; forming a hard mask pattern over the insulation layer; etching a portion of the insulation layer using the hard mask pattern as an etch mask to form an opening; forming spacers over sidewalls of the hard mask pattern and the insulation layer patterned by the etching; etching a remaining portion of the insulation layer to form a contact hole exposing a portion of the bottom structure; and removing the spacers and the hard mask pattern.
摘要翻译：提供了一种在半导体器件中形成接触孔的方法。在半导体器件中形成接触孔的方法包括：在底部结构上形成绝缘层; 在绝缘层上形成硬掩模图案; 使用硬掩模图案作为蚀刻掩模蚀刻绝缘层的一部分以形成开口; 在硬掩模图案的侧壁和通过蚀刻图案化的绝缘层上形成间隔物; 蚀刻绝缘层的剩余部分以形成暴露底部结构的一部分的接触孔; 并且去除间隔物和硬掩模图案。

18. 发明授权

US07074722B2 Method for fabricating semiconductor device with fine pattern 有权
标题翻译：具有精细图案的半导体器件的制造方法
公开(公告)号：US07074722B2
公开(公告)日：2006-07-11
申请号：US10748613
申请日：2003-12-29
申请人： Min-Suk Lee , Sung-Kwon Lee
发明人： Min-Suk Lee , Sung-Kwon Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/76897 , H01L21/0276 , H01L21/31116 , H01L21/31144 , H01L21/76802
摘要： The present invention relates to a method for fabricating a semiconductor device with a fine pattern. The method includes the steps of: (a) forming a semiconductor substrate structure including a substrate, a nitride layer for forming a hard mask, a plurality of conductive patterns, an etch stop layer, an inter-layer insulation layer, an anti-reflective coating (ARC) layer and a photoresist pattern; (b) selectively etching the ARC layer and the nitride layer with use of the photoresist pattern as an etch mask to form a hard mask; (c) removing the photoresist pattern and the ARC layer; (d) etching the inter-layer insulation layer disposed between the conductive patterns by using the hard mask as an etch mask to form a contact hole exposing the etch stop layer; (e) removing the etch stop layer formed at a bottom area of the contact hole to expose the substrate; and (f) forming a plug electrically contacted to the exposed substrate, wherein the steps (b) and (d) to (e) proceeds in an in situ condition.
摘要翻译：本发明涉及一种具有精细图案的半导体器件的制造方法。该方法包括以下步骤：（a）形成半导体衬底结构，其包括衬底，用于形成硬掩模的氮化物层，多个导电图案，蚀刻停止层，层间绝缘层，抗反射层涂层（ARC）层和光致抗蚀剂图案; （b）使用光致抗蚀剂图案作为蚀刻掩模来选择性地蚀刻ARC层和氮化物层以形成硬掩模; （c）去除光致抗蚀剂图案和ARC层; （d）通过使用硬掩模作为蚀刻掩模蚀刻设置在导电图案之间的层间绝缘层，以形成暴露蚀刻停止层的接触孔; （e）去除形成在接触孔的底部区域处的蚀刻停止层，以露出衬底; 和（f）形成与暴露的基底电接触的插塞，其中步骤（b）和（d）至（e）以原位状态进行。

19. 发明授权

US06995056B2 Method for fabricating semiconductor device capable of preventing damage by wet cleaning process 有权
标题翻译：制造能够防止湿式清洗工艺损坏的半导体装置的方法
公开(公告)号：US06995056B2
公开(公告)日：2006-02-07
申请号：US10880953
申请日：2004-06-29
申请人： Sung-Kwon Lee , Min-Suk Lee
发明人： Sung-Kwon Lee , Min-Suk Lee
IPC分类号： H01L21/8249 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/76897 , H01L21/76831 , H01L21/76832 , H01L27/10855 , H01L27/10888
摘要： A method for fabricating a semiconductor device capable of preventing an inter-layer insulation layer from being damaged during a wet cleaning process. The method includes the steps of: forming a plurality of conductive structures on a substrate; forming an etch stop layer and a flowable insulation layer on the plurality of conductive structures subsequently; forming a photoresist pattern on the flowable insulation layer; forming a plurality of contact holes by etching the flowable insulation layer with use of the photoresist pattern as an etch mask, thereby exposing portions of the etch stop layer; forming at least one barrier layer on the contact holes; removing said at least one barrier layer and the etch stop layer disposed at each bottom portion of the contact holes to thereby expose the substrate; and cleaning the contact holes.
摘要翻译：一种制造半导体器件的方法，其能够防止层间绝缘层在湿式清洗过程中被损坏。该方法包括以下步骤：在衬底上形成多个导电结构; 随后在所述多个导电结构上形成蚀刻停止层和可流动的绝缘层; 在可流动绝缘层上形成光致抗蚀剂图案; 通过使用光致抗蚀剂图案作为蚀刻掩模蚀刻可流动绝缘层来形成多个接触孔，从而暴露部分蚀刻停止层; 在所述接触孔上形成至少一个阻挡层; 去除设置在接触孔的每个底部处的所述至少一个阻挡层和蚀刻停止层，从而使基板露出; 并清洁接触孔。

20. 发明授权

US06784084B2 Method for fabricating semiconductor device capable of reducing seam generations 失效
标题翻译：制造半导体器件的方法，能够减少缝合次数
公开(公告)号：US06784084B2
公开(公告)日：2004-08-31
申请号：US10607052
申请日：2003-06-27
申请人： Hyeok Kang , Sung-Kwon Lee , Min-Suk Lee
发明人： Hyeok Kang , Sung-Kwon Lee , Min-Suk Lee
IPC分类号： H01L213205
CPC分类号： H01L21/76897 , H01L21/31144 , Y10S438/902 , Y10S438/906 , Y10S438/976
摘要： The present invention is related to a method for fabricating a semiconductor device capable of preventing occurrences of void and seam phenomena caused by a negative slope of an insulation layer or a bowing profile phenomenon in a cross-sectioned etch profile of a contact hole. To achieve this effect, the attack barrier layer or the capping layer is additionally deposited on the profile containing self-aligned contact holes in order to prevent an undercut of the inter-layer insulation layer, which is a main cause of the seam generations. Also, the attack barrier layer has a function of preventing the inter-layer insulation layer from being attacked during the wet cleaning/etching process. Ultimately, it is possible to improve device characteristics with the prevention of the seam generations.
摘要翻译：本发明涉及一种用于制造半导体器件的方法，该半导体器件能够防止在接触孔的横截面蚀刻轮廓中由绝缘层的负斜率或弓形轮廓现象引起的空隙和接缝现象的发生。为了达到这个效果，攻击阻挡层或覆盖层另外沉积在包含自对准接触孔的轮廓上，以防止层间绝缘层的底切，这是缝隙世代的主要原因。此外，攻击阻挡层具有防止层间绝缘层在湿式清洗/蚀刻工艺期间被侵蚀的功能。最终，可以通过防止接缝世代改善设备特性。

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