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11. 发明申请

US20060057807A1 Method of fabricating a semiconductor device having a silicon oxide layer, a method of fabricating a semiconductor device having dual spacers, a method of forming a silicon oxide layer on a substrate, and a method of forming dual spacers on a conductive material layer 有权
公开(公告)号：US20060057807A1
公开(公告)日：2006-03-16
申请号：US11269599
申请日：2005-11-09
申请人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Min-Chul Sun , Sun-Pil Youn
发明人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Min-Chul Sun , Sun-Pil Youn
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/02164 , H01L21/02211 , H01L21/02271 , H01L21/02362 , H01L21/31612 , H01L27/115
摘要： A method of fabricating a semiconductor device that includes dual spacers is provided. A nitrogen atmosphere may be created and maintained in a reaction chamber by supplying a nitrogen source gas. A silicon source gas and an oxygen source gas may then be supplied to the reaction chamber to deposit a silicon oxide layer on a semiconductor substrate, which may include a conductive material layer. A silicon nitride layer may then be formed on the silicon oxide layer by performing a general CVD process. Next, the silicon nitride layer may be etched until the silicon oxide layer is exposed. Because of the difference in etching selectivity between silicon nitride and silicon oxide, portions of the silicon nitride layer may remain on sidewalls of the conductive material layer. As a result, dual spacers formed of a silicon oxide layer and a silicon nitride layer may be formed on the sidewalls.

12. 发明授权

US07005367B2 Method of fabricating a semiconductor device having a silicon oxide layer, a method of fabricating a semiconductor device having dual spacers, a method of forming a silicon oxide layer on a substrate, and a method of forming dual spacers on a conductive material layer 有权
标题翻译：制造具有氧化硅层的半导体器件的方法，制造具有双间隔物的半导体器件的方法，在衬底上形成氧化硅层的方法以及在导电材料层上形成双间隔物的方法
公开(公告)号：US07005367B2
公开(公告)日：2006-02-28
申请号：US10612041
申请日：2003-07-03
申请人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Min-Chul Sun , Sun-Pil Youn
发明人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Min-Chul Sun , Sun-Pil Youn
IPC分类号： H01L21/441
CPC分类号： H01L27/11521 , H01L21/02164 , H01L21/02211 , H01L21/02271 , H01L21/02362 , H01L21/31612 , H01L27/115
摘要： A method of fabricating a semiconductor device that includes dual spacers is provided. A nitrogen atmosphere may be created and maintained in a reaction chamber by supplying a nitrogen source gas. A silicon source gas and an oxygen source gas may then be supplied to the reaction chamber to deposit a silicon oxide layer on a semiconductor substrate, which may include a conductive material layer. A silicon nitride layer may then be formed on the silicon oxide layer by performing a general CVD process. Next, the silicon nitride layer may be etched until the silicon oxide layer is exposed. Because of the difference in etching selectivity between silicon nitride and silicon oxide, portions of the silicon nitride layer may remain on sidewalls of the conductive material layer. As a result, dual spacers formed of a silicon oxide layer and a silicon nitride layer may be formed on the sidewalls.
摘要翻译：提供一种制造包括双间隔件的半导体器件的方法。可以通过供应氮源气体在反应室中产生和保持氮气氛。然后可以将硅源气体和氧源气体供应到反应室以在可包括导电材料层的半导体衬底上沉积氧化硅层。然后可以通过执行一般CVD工艺在氧化硅层上形成氮化硅层。接下来，可以蚀刻氮化硅层直到氧化硅层露出。由于氮化硅和氧化硅之间的蚀刻选择性的差异，氮化硅层的部分可能残留在导电材料层的侧壁上。结果，可以在侧壁上形成由氧化硅层和氮化硅层形成的双重间隔物。

13. 发明申请

US20120319201A1 SEMICONDUCTOR DEVICES HAVING VERTICAL DEVICE AND NON-VERTICAL DEVICE AND METHODS OF FORMING THE SAME 有权
标题翻译：具有垂直装置和非垂直装置的半导体装置及其形成方法
公开(公告)号：US20120319201A1
公开(公告)日：2012-12-20
申请号：US13412760
申请日：2012-03-06
申请人： Min-Chul Sun , Byung-Gook Park
发明人： Min-Chul Sun , Byung-Gook Park
IPC分类号： H01L27/092
CPC分类号： H01L27/1104 , H01L21/823487 , H01L21/823885 , H01L27/092 , H01L29/7827
摘要： In a semiconductor device, a vertical transistor comprises: a first diffusion region on a substrate; a channel region on the first diffusion region and extending in a vertical direction; a second diffusion region on the channel region; and a gate electrode at a sidewall of, and insulated from, the channel region. A horizontal transistor is positioned on the substrate, the horizontal transistor comprising: a first diffusion region and a second diffusion region on the substrate and spaced apart from each other; a channel region on the substrate between the first diffusion region and the second diffusion region; and a gate electrode on the channel region and isolated from the channel region. A portion of a gate electrode of the vertical transistor and a portion of the gate electrode of the horizontal transistor are at a same vertical position in the vertical direction relative to the substrate.
摘要翻译：在半导体器件中，垂直晶体管包括：衬底上的第一扩散区; 在所述第一扩散区域上的沿垂直方向延伸的沟道区域; 沟道区上的第二扩散区; 以及在沟道区的侧壁处和绝缘的栅电极。水平晶体管位于衬底上，水平晶体管包括：在衬底上的第一扩散区和第二扩散区，彼此间隔开; 在所述第一扩散区域和所述第二扩散区域之间的衬底上的沟道区域; 以及沟道区上的栅极，并与沟道区分离。垂直晶体管的栅电极的一部分和水平晶体管的栅电极的一部分在垂直方向上相对于衬底处于相同的垂直位置。

14. 发明申请

US20130178048A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING BURIED WIRING AND RELATED DEVICE 有权
标题翻译：具有布线接线的半导体器件的制造方法及相关器件
公开(公告)号：US20130178048A1
公开(公告)日：2013-07-11
申请号：US13550814
申请日：2012-07-17
申请人： Min-Chul Sun , Byung-Gook Park
发明人： Min-Chul Sun , Byung-Gook Park
IPC分类号： H01L21/20
CPC分类号： H01L21/76889 , H01L21/28518 , H01L21/743 , H01L21/76843 , H01L21/76855 , H01L23/485 , H01L23/535 , H01L27/0688 , H01L27/1108 , H01L27/1157 , H01L27/11582 , H01L27/2409 , H01L2924/0002 , H01L2924/00
摘要： According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes forming a sacrificial pattern having SiGe on a crystalline silicon substrate. A body having crystalline silicon is formed on the sacrificial pattern. At least one active element is formed on the body. An insulating layer is formed to cover the sacrificial pattern, the body, and the active element. A contact hole is formed to expose the sacrificial pattern through the insulating layer. A void space is formed by removing the sacrificial pattern. An amorphous silicon layer is formed in the contact hole and the void space. The amorphous silicon layer is transformed into a metal silicide layer.
摘要翻译：根据发明构思的示例性实施例，制造半导体器件的方法包括在晶体硅衬底上形成具有SiGe的牺牲图案。在牺牲图案上形成具有晶体硅的主体。在身体上形成至少一个活动元件。形成绝缘层以覆盖牺牲图案，主体和有源元件。形成接触孔以通过绝缘层露出牺牲图案。通过去除牺牲图案形成空隙。在接触孔和空隙空间中形成非晶硅层。将非晶硅层转变成金属硅化物层。

15. 发明申请

US20090256214A1 Semiconductor device and associated methods 审中-公开
标题翻译：半导体器件及相关方法
公开(公告)号：US20090256214A1
公开(公告)日：2009-10-15
申请号：US12385574
申请日：2009-04-13
申请人： Min-Chul Sun , Dong-Suk Shin , Jung-Deog Lee
发明人： Min-Chul Sun , Dong-Suk Shin , Jung-Deog Lee
IPC分类号： H01L29/78
CPC分类号： H01L27/088 , H01L21/76897 , H01L29/665 , H01L29/6656
摘要： A semiconductor device and process of fabricating the same, the semiconductor device including a semiconductor substrate, a gate insulating layer on the semiconductor substrate, a gate electrode having sidewalls, on the gate insulating layer, first spacers on the sidewalls of the gate electrode, a source/drain region in the semiconductor substrate, aligned with the sidewalls, a silicide layer on the gate electrode, a silicide layer on the source/drain region, and second spacers covering the first spacers and end parts of a surface of the silicide layer on the source drain region.
摘要翻译：一种半导体器件及其制造方法，半导体器件包括半导体衬底，半导体衬底上的栅极绝缘层，具有侧壁的栅电极，栅极绝缘层，栅电极的侧壁上的第一间隔物，源极/漏极区域，与侧壁对准，栅极上的硅化物层，源极/漏极区域上的硅化物层，以及覆盖第一间隔物和硅化物层的表面的端部的第二间隔物，源极漏极区域。

16. 发明申请

US20070102779A1 Differential mechanical stress-producing regions for integrated circuit field effect transistors 有权
标题翻译：用于集成电路场效应晶体管的差分机械应力产生区域
公开(公告)号：US20070102779A1
公开(公告)日：2007-05-10
申请号：US11268131
申请日：2005-11-07
申请人： Min-Chul Sun , Young Teh
发明人： Min-Chul Sun , Young Teh
IPC分类号： H01L31/00
CPC分类号： H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L29/7842 , H01L29/7843 , H01L29/7847
摘要： Integrated circuit field effect transistors include a substrate, an isolation region in the substrate that defines an active region in the substrate, spaced apart source/drain regions in the active region, a channel region in the active region between the spaced apart source/drain regions and an insulated gate on the channel region. A differential mechanical stress-producing region is configured to produce different mechanical stress in the channel region adjacent the isolation region compared to remote from the isolation region. The differential mechanical stress-producing region may be formed using patterned stress management films, patterned stress-changing implants and/or patterned silicide films, and can reduce undesired comer effects. Related fabrication methods also are described.
摘要翻译：集成电路场效应晶体管包括衬底，衬底中的限定衬底中的有源区域的隔离区域，有源区域中的间隔开的源极/漏极区域，在间隔开的源极/漏极区域之间的有源区域中的沟道区域和沟道区域上的绝缘栅极。差分机械应力产生区域被配置为在远离隔离区域的区域中在邻近隔离区域的通道区域中产生不同的机械应力。可以使用图案化应力管理膜，图案化的应力改变植入物和/或图案化硅化物膜形成差分机械应力产生区域，并且可以减少不期望的角落效应。还描述了相关的制造方法。

17. 发明授权

US08928080B2 Field-effect transistor having back gate and method of fabricating the same 有权
标题翻译：具有背栅的场效晶体管及其制造方法
公开(公告)号：US08928080B2
公开(公告)日：2015-01-06
申请号：US13554066
申请日：2012-07-20
申请人： Min-Chul Sun , Byung-Gook Park
发明人： Min-Chul Sun , Byung-Gook Park
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L29/0673 , H01L29/7854 , H01L29/78648 , H01L29/78696
摘要： A back-bias region is disposed on a substrate. A buried insulating layer covers the substrate and the back-bias region. A body is formed on the buried insulating layer and partially overlaps the back-bias region. A drain is in contact with the body. A gate electrode covers top and lateral surfaces of the body.
摘要翻译：背面偏置区域设置在基板上。掩埋绝缘层覆盖基板和背偏置区域。在掩埋绝缘层上形成一体并且部分地与背偏置区重叠。排水管与身体接触。栅电极覆盖身体的顶表面和侧表面。

18. 发明授权

US08557691B2 Method of fabricating semiconductor device having buried wiring and related device 有权
标题翻译：具有埋地布线的半导体器件及其相关器件的制造方法
公开(公告)号：US08557691B2
公开(公告)日：2013-10-15
申请号：US13550814
申请日：2012-07-17
申请人： Min-Chul Sun , Byung-Gook Park
发明人： Min-Chul Sun , Byung-Gook Park
IPC分类号： H01L21/425
CPC分类号： H01L21/76889 , H01L21/28518 , H01L21/743 , H01L21/76843 , H01L21/76855 , H01L23/485 , H01L23/535 , H01L27/0688 , H01L27/1108 , H01L27/1157 , H01L27/11582 , H01L27/2409 , H01L2924/0002 , H01L2924/00
摘要： According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes forming a sacrificial pattern having SiGe on a crystalline silicon substrate. A body having crystalline silicon is formed on the sacrificial pattern. At least one active element is formed on the body. An insulating layer is formed to cover the sacrificial pattern, the body, and the active element. A contact hole is formed to expose the sacrificial pattern through the insulating layer. A void space is formed by removing the sacrificial pattern. An amorphous silicon layer is formed in the contact hole and the void space. The amorphous silicon layer is transformed into a metal silicide layer.
摘要翻译：根据发明构思的示例性实施例，制造半导体器件的方法包括在晶体硅衬底上形成具有SiGe的牺牲图案。在牺牲图案上形成具有晶体硅的主体。在身体上形成至少一个活动元件。形成绝缘层以覆盖牺牲图案，主体和有源元件。形成接触孔以通过绝缘层露出牺牲图案。通过去除牺牲图案形成空隙。在接触孔和空隙空间中形成非晶硅层。将非晶硅层转变成金属硅化物层。

19. 发明授权

US08481392B1 Methods of fabricating semiconductor device using high-K layer for spacer etch stop and related devices 有权
标题翻译：使用高K层制备半导体器件用于间隔蚀刻停止和相关器件的方法
公开(公告)号：US08481392B1
公开(公告)日：2013-07-09
申请号：US13542717
申请日：2012-07-06
申请人： Min-Chul Sun , Byung-Gook Park
发明人： Min-Chul Sun , Byung-Gook Park
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Methods of fabricating a semiconductor device, and related devices, include forming a gate electrode on a substrate, forming a first buffer layer, a second buffer layer and a third buffer layer on side surfaces of the gate electrode and on the substrate near the gate electrode, forming a spacer covering the side surfaces of the gate electrode on the third buffer layer, the third buffer layer on the substrate being exposed, exposing the second buffer layer on the substrate by removing the exposed third buffer layer, exposing the first buffer layer on the substrate by removing the exposed second buffer layer, forming deep junction in the substrate using the spacer as a mask, and removing the spacer. The third buffer layer is a material layer having a higher dielectric constant than the second buffer layer. The spacer includes a material layer different than the third, second and first buffer layers.
摘要翻译：制造半导体器件的方法及相关器件包括在衬底上形成栅电极，在栅电极的侧表面和栅电极附近形成第一缓冲层，第二缓冲层和第三缓冲层形成覆盖第三缓冲层上的栅电极的侧表面的间隔物，衬底上的第三缓冲层被暴露，通过去除暴露的第三缓冲层而将第二缓冲层暴露在衬底上，将第一缓冲层暴露在通过去除暴露的第二缓冲层，在衬底中使用间隔物作为掩模形成深结，并且去除衬垫。第三缓冲层是具有比第二缓冲层更高的介电常数的材料层。间隔物包括与第三，第二和第一缓冲层不同的材料层。

20. 发明申请

US20130171810A1 METHODS OF FABRICATING SEMICONDUCTOR DEVICE USING HIGH-K LAYER FOR SPACER ETCH STOP AND RELATED DEVICES 有权
标题翻译：使用高K层制备半导体器件以进行间隔停止和相关器件的方法
公开(公告)号：US20130171810A1
公开(公告)日：2013-07-04
申请号：US13542717
申请日：2012-07-06
申请人： Min-Chul Sun , Byung-Gook Park
发明人： Min-Chul Sun , Byung-Gook Park
IPC分类号： H01L21/425
CPC分类号： H01L29/6653 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Methods of fabricating a semiconductor device, and related devices, include forming a gate electrode on a substrate, forming a first buffer layer, a second buffer layer and a third buffer layer on side surfaces of the gate electrode and on the substrate near the gate electrode, forming a spacer covering the side surfaces of the gate electrode on the third buffer layer, the third buffer layer on the substrate being exposed, exposing the second buffer layer on the substrate by removing the exposed third buffer layer, exposing the first buffer layer on the substrate by removing the exposed second buffer layer, forming deep junction in the substrate using the spacer as a mask, and removing the spacer. The third buffer layer is a material layer having a higher dielectric constant than the second buffer layer. The spacer includes a material layer different than the third, second and first buffer layers.
摘要翻译：制造半导体器件的方法及相关器件包括在衬底上形成栅电极，在栅电极的侧表面和栅电极附近形成第一缓冲层，第二缓冲层和第三缓冲层形成覆盖第三缓冲层上的栅电极的侧表面的间隔物，衬底上的第三缓冲层被暴露，通过去除暴露的第三缓冲层而将第二缓冲层暴露在衬底上，将第一缓冲层暴露在通过去除暴露的第二缓冲层，在衬底中使用间隔物作为掩模形成深结，并且去除衬垫。第三缓冲层是具有比第二缓冲层更高的介电常数的材料层。间隔物包括与第三，第二和第一缓冲层不同的材料层。

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