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    • 11. 发明授权
    • Symmetrical differential sensing method and system for STT MRAM
    • STT MRAM对称差分感测方法及系统
    • US09076540B2
    • 2015-07-07
    • US13592597
    • 2012-08-23
    • David MuellerWolf AllersMihail Jefremow
    • David MuellerWolf AllersMihail Jefremow
    • G11C11/00G11C11/16G11C7/02G11C7/12G11C29/02G11C29/50
    • G11C11/1673G11C7/02G11C7/12G11C11/16G11C11/1659G11C29/021G11C29/028G11C2029/5006
    • The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In one example, a system for reading a memory cell includes a sense path and an inverse path. A reference current is provided through the sense path and is sampled via a first sampling element in the sense path, and a cell current from the memory cell is provided through the inverse sense path and is sampled via a second sampling element in the inverse sense path. Subsequently, the memory cell is disconnected from the inverse sense path, the cell current is provided through the sense path, the reference source is disconnected from the sense path, and the reference current is provided through the inverse sense path. The output levels are then determined by the cell and reference currents working against the sampled reference and sampled cell currents.
    • 本发明涉及用于读取存储器单元,特别是STT MRAM的方法和系统。 在一个示例中,用于读取存储器单元的系统包括感测路径和反向路径。 通过感测路径提供参考电流,并且通过感测路径中的第一采样元件进行采样,并且通过反向感测路径提供来自存储器单元的单元电流,并且经由反向感测路径中的第二采样元件进行采样 。 随后,存储器单元与反向感测路径断开,通过感测路径提供单元电流,参考源与感测路径断开,并通过反向感测路径提供参考电流。 然后,输出电平由电池和参考电流根据采样的参考和采样单元电流工作来确定。
    • 12. 发明申请
    • Symmetrical Differential Sensing Method and System for STT MRAM
    • STT MRAM对称差分传感方法及系统
    • US20140056059A1
    • 2014-02-27
    • US13592597
    • 2012-08-23
    • David MuellerWolf AllersMihail Jefremow
    • David MuellerWolf AllersMihail Jefremow
    • G11C7/02G11C11/16
    • G11C11/1673G11C7/02G11C7/12G11C11/16G11C11/1659G11C29/021G11C29/028G11C2029/5006
    • The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In one example, a system for reading a memory cell includes a sense path and an inverse path. A reference current is provided through the sense path and is sampled via a first sampling element in the sense path, and a cell current from the memory cell is provided through the inverse sense path and is sampled via a second sampling element in the inverse sense path. Subsequently, the memory cell is disconnected from the inverse sense path, the cell current is provided through the sense path, the reference source is disconnected from the sense path, and the reference current is provided through the inverse sense path. The output levels are then determined by the cell and reference currents working against the sampled reference and sampled cell currents.
    • 本发明涉及用于读取存储器单元,特别是STT MRAM的方法和系统。 在一个示例中,用于读取存储器单元的系统包括感测路径和反向路径。 通过感测路径提供参考电流,并且通过感测路径中的第一采样元件进行采样,并且通过反向感测路径提供来自存储器单元的单元电流,并且经由反向感测路径中的第二采样元件进行采样 。 随后,存储器单元与反向感测路径断开,通过感测路径提供单元电流,参考源与感测路径断开,并通过反向感测路径提供参考电流。 然后,输出电平由电池和参考电流根据采样的参考和采样单元电流工作来确定。
    • 13. 发明申请
    • SELF TIMED CURRENT INTEGRATING SCHEME EMPLOYING LEVEL AND SLOPE DETECTION
    • 自适应电流积分方案采用水平和坡度检测
    • US20120126783A1
    • 2012-05-24
    • US12951190
    • 2010-11-22
    • Mihail JefremowThomas KernUllrich MenczigarUlrich Backhausen
    • Mihail JefremowThomas KernUllrich MenczigarUlrich Backhausen
    • G01R25/00
    • G11C7/02G11C16/28
    • Some embodiments of the invention relate to a sense amplifier configured to determine the slope of a bitline charging voltage and to utilize the determined slope in combination with a voltage level sensing scheme to aid in reading data from a memory cell associated with the bitline. In particular, a sense amplifier circuit is configured to determine a slope of a bit line charging voltage and based upon the determined slope to adjust the slope of the bitline voltage (e.g., by adding a dynamic slope dependent current to a memory cell current configured to charge the bitline) provided to a sense amplifier. By adjusting the slope of the bitline voltage, the charging speed of memory cells in a low resistive state (e.g., having a high cell current and therefore a good SNR) can be increased.
    • 本发明的一些实施例涉及被配置为确定位线充电电压的斜率并且将确定的斜率与电压电平感测方案结合使用以帮助从与位线相关联的存储器单元读取数据的读出放大器。 特别地,读出放大器电路被配置为确定位线充电电压的斜率并且基于所确定的斜率来调整位线电压的斜率(例如,通过将动态斜率相关电流加到配置为 提供给读出放大器的位线)。 通过调整位线电压的斜率,可以提高处于低电阻状态(例如,具有高电池电流,因此具有良好SNR)的存储器单元的充电速度。
    • 14. 发明授权
    • Self timed current integrating scheme employing level and slope detection
    • 采用电平和斜率检测的自定时电流积分方案
    • US08559243B2
    • 2013-10-15
    • US12951190
    • 2010-11-22
    • Mihail JefremowThomas KernUllrich MenczigarUlrich Backhausen
    • Mihail JefremowThomas KernUllrich MenczigarUlrich Backhausen
    • G11C7/06
    • G11C7/02G11C16/28
    • Some embodiments of the invention relate to a sense amplifier configured to determine the slope of a bitline charging voltage and to utilize the determined slope in combination with a voltage level sensing scheme to aid in reading data from a memory cell associated with the bitline. In particular, a sense amplifier circuit is configured to determine a slope of a bit line charging voltage and based upon the determined slope to adjust the slope of the bitline voltage (e.g., by adding a dynamic slope dependent current to a memory cell current configured to charge the bitline) provided to a sense amplifier. By adjusting the slope of the bitline voltage, the charging speed of memory cells in a low resistive state (e.g., having a high cell current and therefore a good SNR) can be increased.
    • 本发明的一些实施例涉及被配置为确定位线充电电压的斜率并且将确定的斜率与电压电平感测方案结合使用以帮助从与位线相关联的存储器单元读取数据的读出放大器。 特别地,读出放大器电路被配置为确定位线充电电压的斜率并且基于所确定的斜率来调整位线电压的斜率(例如,通过将动态斜率相关电流加到配置为 提供给读出放大器的位线)。 通过调整位线电压的斜率,可以提高处于低电阻状态(例如,具有高电池电流,因此具有良好SNR)的存储器单元的充电速度。