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    • 12. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08773938B2
    • 2014-07-08
    • US13064915
    • 2011-04-26
    • Toshiro Sasaki
    • Toshiro Sasaki
    • G11C5/14
    • G06F1/26G11C5/145G11C16/30H01L24/06H01L2224/05554
    • A semiconductor device includes a drive circuit that outputs a drive signal to drive an external device; a voltage output circuit that outputs a first voltage and a second voltage that is larger than the first voltage; a selector that, when supplying a power supply voltage to the drive circuit, selects the first voltage and, when supplying a power supply voltage to an internal device, selects the second voltage; and a step-up circuit that, when the first voltage selected by the selector is input, boosts the first voltage to a third voltage and outputs the third voltage as the power supply voltage to the drive circuit and, when the second voltage selected by the selector is inputted, boosts the second voltage to a fourth voltage and outputs the fourth voltage as the power supply voltage to the internal device.
    • 半导体器件包括:驱动电路,其输出用于驱动外部器件的驱动信号; 电压输出电路,其输出大于所述第一电压的第一电压和第二电压; 选择器,当向所述驱动电路供给电源电压时,选择所述第一电压,并且当向所述内部装置供应电源电压时,选择所述第二电压; 以及升压电路,当输入由选择器选择的第一电压时,将第一电压升压到第三电压,并将作为电源电压的第三电压输出到驱动电路,并且当由第二电压选择 选择器被输入,将第二电压升压到第四电压,并将第四电压作为电源电压输出到内部装置。
    • 17. 发明授权
    • Semiconductor memory device having a common column decoder shared by
plurality of banks
    • 半导体存储器件具有由多个存储体共享的公共列解码器
    • US6163496A
    • 2000-12-19
    • US418040
    • 1999-10-14
    • Toshiro SasakiYuichi Matsushita
    • Toshiro SasakiYuichi Matsushita
    • G11C11/407G11C7/10G11C11/401G11C8/00
    • G11C7/1006
    • A column switching circuit that connects a bit line pair and sub-data buses is constituted of first through fourth N transistors. The first and third N transistors are connected in series to a first bit line of the bit line pair whereas the second and fourth N transistors are connected in series to the second bit line of the bit line pair. The gate of the first N transistor and the gate of the second N transistor are connected to commonly receive a column switch selection signal. The gate of the third N transistor and the gate of the fourth N transistor are commonly connected to a column line. By adopting this structure, the generation of a through current is prevented from occurring between the bit line pair and the sub-data buses to result in a reduction in power consumption and miniaturization of the chip is achieved.
    • 连接位线对和子数据总线的列切换电路由第一至第四N晶体管构成。 第一和第三N晶体管与位线对的第一位线串联连接,而第二和第三N晶体管串联连接到位线对的第二位线。 第一N晶体管的栅极和第二N晶体管的栅极被连接以共同接收列开关选择信号。 第三N晶体管的栅极和第四N晶体管的栅极共同连接到列线。 通过采用这种结构,防止在位线对和子数据总线之间产生直通电流,导致功耗的降低,并且实现了芯片的小型化。