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11. 发明授权

US08154268B2 Switching regulator with balanced control configuration with filtering and referencing to eliminate compensation 有权
标题翻译：开关稳压器具有平衡控制配置，具有滤波和参考，以消除补偿
公开(公告)号：US08154268B2
公开(公告)日：2012-04-10
申请号：US12324368
申请日：2008-11-26
申请人： Rhys S. A. Philbrick , Matthew B. Harris , Steven P. Laur
发明人： Rhys S. A. Philbrick , Matthew B. Harris , Steven P. Laur
IPC分类号： G05F1/565 , G05F1/575
CPC分类号： H02M3/156 , H02M3/158
摘要： A controller for a switching regulator is disclosed including a sense circuit, an error amplifier circuit, a filter and reference circuit, and a comparator circuit. The switching regulator includes a pulse switch circuit coupled to an output inductor for developing an output voltage. The sense circuit provides a sense signal indicative of current through the output inductor. The error amplifier circuit develops an error signal indicative of error of the output voltage. The filter and reference circuit high pass filters the sense signal to provide a filtered sense signal, and references the filtered sense signal and the error signal to a common DC level. The comparator circuit develops a pulse control signal used to control switching of the pulse switch circuit based on comparing the error signal with the filtered sense signal.
摘要翻译：公开了一种用于开关调节器的控制器，其包括感测电路，误差放大器电路，滤波器和参考电路以及比较器电路。开关稳压器包括耦合到输出电感器以产生输出电压的脉冲开关电路。感测电路提供指示通过输出电感器的电流的感测信号。误差放大器电路产生表示输出电压误差的误差信号。滤波器和参考电路高通滤波感测信号以提供滤波的感测信号，并将滤波的感测信号和误差信号引用到公共的DC电平。比较器电路基于将误差信号与滤波的感测信号进行比较，形成用于控制脉冲开关电路的开关的脉冲控制信号。

12. 发明授权

US07061215B2 Cascadable current-mode regulator 失效
标题翻译：级联电流模式调节器
公开(公告)号：US07061215B2
公开(公告)日：2006-06-13
申请号：US10739757
申请日：2003-12-18
申请人： Matthew B. Harris
发明人： Matthew B. Harris
IPC分类号： G05F1/40
CPC分类号： H02J1/102 , H02M3/1584
摘要： A cascadable power regulator including a programmable delay unit and PWM control logic. The programmable delay unit initiates a delay period in response to a digital input signal and asserts a digital output signal upon expiration of the delay period. The PWM control logic controls a PWM cycle in response to the digital input signal and in response to an output control condition. The cascadable regulator uses digital signals to communicate between channels. Digital signals are not prone to the same kind of signal degradation or noise susceptibility as analog signals. Thus, the number of phases is not limited, the physical separation between the regulators is not limited, and the switching frequency is not as limited. There is no clock signal from a separate controller so that the controller is a relatively simple, low-cost device. Since there is no clock, a unique self-oscillating system is achieved using the cascadable regulator.
摘要翻译：包括可编程延迟单元和PWM控制逻辑的级联功率调节器。可编程延迟单元响应于数字输入信号启动延迟周期，并在延迟周期期满时断言数字输出信号。 PWM控制逻辑响应于数字输入信号并且响应于输出控制条件来控制PWM周期。可级联调节器使用数字信号在通道之间通信。数字信号不容易产生与模拟信号相同的信号劣化或噪声敏感性。因此，相数不受限制，调节器之间的物理分离不受限制，开关频率不受限制。没有来自单独控制器的时钟信号，使得控制器是相对简单的低成本设备。由于没有时钟，使用可级联调节器实现了独特的自振荡系统。

13. 发明授权

US5714886A Method of calibrating the trip point of an overload relay 失效
标题翻译：校准过载继电器跳闸点的方法
公开(公告)号：US5714886A
公开(公告)日：1998-02-03
申请号：US773382
申请日：1996-12-26
申请人： Matthew B. Harris
发明人： Matthew B. Harris
IPC分类号： G01R35/00 , H02H3/00
CPC分类号： G01R35/005 , H02H3/006
摘要： A method of calibrating the selectable trip points of an overload relay wherein a neural network is used in the calibration process. The calibration method involves precisely positioning an indicia comprised of a number of graduation marks or symbols each representing a particular trip point and having a range and spacing unique to the characteristics of an overload detection circuit of a particular overload relay. The indicia is calibrated with respect to predetermined positions of a trip point indicator and fixed with respect to the predetermined positions of the trip point indicator. The range and spacing of the indicia graduations is derived from the neural networks learned trip point values and from trip point values obtained from the particular overload relay being calibrated.
摘要翻译：一种校准过载继电器的可选跳闸点的方法，其中在校准过程中使用神经网络。校准方法包括精确地定位由多个刻度标记或符号构成的标记，每个刻痕或符号表示特定的跳变点，并且具有与特定过载继电器的过载检测电路的特性相独立的范围和间隔。标记相对于跳闸点指示器的预定位置被校准，并相对于跳闸点指示器的预定位置固定。标记刻度的范围和间距来自神经网络学习的跳变点值和从被校准的特定过载继电器获得的跳变点值。

14. 发明授权

US5587662A Method and apparatus for nondisruptively measuring line impedance at frequencies which are relatively close to the line frequency 失效
标题翻译：用于在相对接近线路频率的频率处非线性测量线路阻抗的方法和装置
公开(公告)号：US5587662A
公开(公告)日：1996-12-24
申请号：US386702
申请日：1995-02-10
申请人： Arthur W. Kelley , Matthew B. Harris
发明人： Arthur W. Kelley , Matthew B. Harris
IPC分类号： G01R27/02 , G01R27/08
CPC分类号： G01R27/02
摘要： Impedance of an energized electrical line which carries electrical current at a predetermined line frequency is nondistruptively measured at frequencies which are above and below the predetermined line frequency. A measurement current is generated at a measurement frequency between, for example, 10 Hz and 30 kHz for a 60 Hz line. The current generator is coupled to the energized electrical line by an isolating circuit which blocks only the predetermined line frequency and frequencies which differ from the predetermined line frequency by substantially less than the predetermined line frequency. For example, a notch filter may be used. A current sensor measures the line current in the energized line at the measurement frequency. A voltage sensor measures the line voltage in the energized electrical line at the measurement frequency. An analyzer determines impedance of the energized line at the measurement frequency. The measurement is repeated over a wide range of frequencies above and below the line frequency. Preferably, the current sensor and voltage sensor use the same current sensor to cancel errors. Improved nondisruptive line impedance measuring is thereby provided.
摘要翻译：在预定线频率以上且低于预定线频率的频率下，以不受干扰地测量承载预定线频率电流的通电电线的阻抗。测量电流以例如10Hz和30kHz之间的测量频率产生，用于60Hz线。电流发生器通过隔离电路耦合到通电的电线，该隔离电路仅阻挡预定线路频率和与预定线路频率不同的频率，其基本上小于预定线路频率。例如，可以使用陷波滤波器。电流传感器以测量频率测量通电线路中的线路电流。电压传感器以测量频率测量通电电线中的线路电压。分析仪测量在测量频率下的通电线路的阻抗。在线频率之上和之下的宽频率范围内重复测量。优选地，电流传感器和电压传感器使用相同的电流传感器来消除误差。从而提供改进的无中断线阻抗测量。

15. 发明授权

US07084613B2 Multiphase DC-DC converter with reduced ripple 失效
标题翻译：具有减少纹波的多相DC-DC转换器
公开(公告)号：US07084613B2
公开(公告)日：2006-08-01
申请号：US10787518
申请日：2004-02-26
申请人： Matthew B. Harris , James W. Leith , Brandon D. Day
发明人： Matthew B. Harris , James W. Leith , Brandon D. Day
IPC分类号： G05F1/59
CPC分类号： H02M3/1584
摘要： A PWM system that minimizes output ripple of a multiphase DC-DC converter which converts N input voltages including at least one dissimilar input voltage. The PWM system includes PWM waveform logic that generates N PWM signals including a PWM signal for each of the N input voltages, and PWM control logic that optimizes relative phases of the N PWM signals based on voltage levels of the N input voltages. Various circuits and/or methods are contemplated for optimizing phase, including, for example, centering pulses for each PWM cycle, distributing pulses based on predetermined optimal phase angles, determining input voltage levels and selecting predetermined optimal phase angles, generating phase signals employing predetermined phase angles, measuring input voltages and calculating optimal phase angles, and using PLL logic or the like to measure and equalize off-times between PWM pulses.
摘要翻译：一种PWM系统，其最小化多相DC-DC转换器的输出纹波，其转换包括至少一个不同输入电压的N个输入电压。 PWM系统包括产生N个PWM信号的PWM波形逻辑，包括N个输入电压中的每一个的PWM信号，以及基于N个输入电压的电压电平优化N个PWM信号的相对相位的PWM控制逻辑。考虑各种电路和/或方法来优化相位，包括例如用于每个PWM周期的对中脉冲，基于预定的最佳相位角分配脉冲，确定输入电压电平并选择预定的最佳相位角，使用预定相位产生相位信号角度，测量输入电压和计算最佳相位角，并使用PLL逻辑等来测量和均衡PWM脉冲之间的关闭时间。

16. 发明授权

US07026798B2 Multi-channel driver interface circuit for increasing phase count in a multi-phase DC-DC converter 有权
标题翻译：多通道驱动器接口电路，用于增加多相DC-DC转换器中的相位计数
公开(公告)号：US07026798B2
公开(公告)日：2006-04-11
申请号：US10887610
申请日：2004-07-09
申请人： Chun Cheung , Matthew B. Harris
发明人： Chun Cheung , Matthew B. Harris
IPC分类号： G05F1/613
CPC分类号： H02M3/1584
摘要： A reduced pin count, dual channel driver interface is configured to interface a supervisory controller with a plurality of multi-phase output channel switching circuits of a multi-phase DC-DC regulator. Each dual channel driver is configured for placement relatively close to output channel sense points, so as to effectively reduce the distance that would otherwise have to be traversed by noise sensitive voltage signals. Sensed current representative signals are processed within the dual driver for current balance between a respective multi driver pair, and are combined to supply the controller with the average current signal of the dual channels. The controller uses this average current-information to adjust respective pulse width modulation signals that are supplied to the dual channel drivers.
摘要翻译：减少引脚数，双通道驱动器接口被配置为使监控器与多相DC-DC调节器的多个多相输出通道切换电路接口。每个双通道驱动器配置为相对靠近输出通道检测点进行放置，以便有效地减少噪声敏感电压信号否则必须穿过的距离。感测的电流代表信号在双驱动器内处理，用于在相应的多驱动器对之间的电流平衡，并被组合以向控制器提供双通道的平均电流信号。控制器使用该平均电流信息来调整提供给双通道驱动器的各个脉冲宽度调制信号。

17. 发明授权

US06897636B2 Method and circuit for scaling and balancing input and output currents in a multi-phase DC-DC converter using different input voltages 失效
标题翻译：用于使用不同输入电压对多相DC-DC转换器中的输入和输出电流进行缩放和平衡的方法和电路
公开(公告)号：US06897636B2
公开(公告)日：2005-05-24
申请号：US10357924
申请日：2003-02-04
申请人： Matthew B. Harris
发明人： Matthew B. Harris
IPC分类号： H02J1/10 , H02M3/158 , G05F1/40
CPC分类号： H02J1/102 , H02M3/1584
摘要： A multi-phase DC—DC converter architecture in which parameters including error signal gains and modulator gains are defined so as to balance multiple converter channel currents, irrespective of whether the converter channels are supplied with the same or different input voltages.
摘要翻译：定义了包括误差信号增益和调制器增益的参数以便平衡多个转换器通道电流的多相DC-DC转换器架构，而不管转换器通道是否具有相同或不同的输入电压。

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