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11. 发明授权

US07793081B2 Implementing instruction set architectures with non-contiguous register file specifiers 有权
标题翻译：用不连续的寄存器文件说明符来实现指令集体系结构
公开(公告)号：US07793081B2
公开(公告)日：2010-09-07
申请号：US12062131
申请日：2008-04-03
申请人： Michael Karl Gschwind , Robert Kevin Montoye , Brett Olsson , John-David Wellman
发明人： Michael Karl Gschwind , Robert Kevin Montoye , Brett Olsson , John-David Wellman
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/30101 , G06F9/30112 , G06F9/30138 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/30174 , G06F9/30181 , G06F9/30185 , G06F9/3802 , G06F9/382 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
摘要： There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous register specifier.
摘要翻译：提供了用于实现具有非连续寄存器文件说明符的指令集架构的方法和计算机程序产品。一种用于处理指令代码的方法包括使用非连续寄存器规范的非连续寄存器说明符来处理固定宽度指令集的固定宽度指令。固定宽度指令包括不连续的寄存器说明符。

12. 发明申请

US20070038848A1 Implementing instruction set architectures with non-contiguous register file specifiers 有权
标题翻译：用不连续的寄存器文件说明符来实现指令集体系结构
公开(公告)号：US20070038848A1
公开(公告)日：2007-02-15
申请号：US11446020
申请日：2006-06-02
申请人： Michael Gschwind , Robert Montoye , Brett Olsson , John-David Wellman
发明人： Michael Gschwind , Robert Montoye , Brett Olsson , John-David Wellman
IPC分类号： G06F9/44
CPC分类号： G06F9/3012 , G06F9/30101 , G06F9/30112 , G06F9/30138 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/30174 , G06F9/30181 , G06F9/30185 , G06F9/3802 , G06F9/382 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
摘要： There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous register specifier.
摘要翻译：提供了用于实现具有非连续寄存器文件说明符的指令集架构的方法和计算机程序产品。一种用于处理指令代码的方法包括使用非连续寄存器规范的非连续寄存器说明符来处理固定宽度指令集的固定宽度指令。固定宽度指令包括不连续的寄存器说明符。

13. 发明申请

US20060236080A1 Reducing the fetch time of target instructions of a predicted taken branch instruction 失效
标题翻译：减少预测的分支指令的目标指令的获取时间
公开(公告)号：US20060236080A1
公开(公告)日：2006-10-19
申请号：US11109001
申请日：2005-04-19
申请人： Richard Doing , Brett Olsson , Kenichi Tsuchiya
发明人： Richard Doing , Brett Olsson , Kenichi Tsuchiya
IPC分类号： G06F15/00
CPC分类号： G06F9/3804 , G06F9/3844
摘要： A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced.
摘要翻译：一种用于减少预测的分支指令的目标指令的获取时间的方法和处理器。缓冲器中的每个条目（这里称为“分支目标缓冲器”）可以存储预测的分支指令的地址和从预测的分支指令的目标地址开始的指令。当从指令高速缓存中取出指令时，使用获取的指令的特定位来对分支目标缓冲器中的特定条目进行索引。将索引条目中的分支指令的地址与从指令高速缓存获取的指令的地址进行比较。如果有匹配，则从该分支指令的目标地址开始的指令直接在分支指令的后面进行调度。以这种方式，减少预测的分支指令的目标指令的获取时间。

14. 发明授权

US06298365B1 Method and system for bounds comparator 有权
标题翻译：边界比较方法和系统
公开(公告)号：US06298365B1
公开(公告)日：2001-10-02
申请号：US09256375
申请日：1999-02-24
申请人： Pradeep Kumar Dubey , Brett Olsson , Ronald Ray Hochsprung , Hunter Ledbetter Scales, III , Keith Everett Diefendorff
发明人： Pradeep Kumar Dubey , Brett Olsson , Ronald Ray Hochsprung , Hunter Ledbetter Scales, III , Keith Everett Diefendorff
IPC分类号： G06F738
CPC分类号： G06F7/026 , G06F7/483
摘要： The invention relates to a method of using a “bounds” comparator scheme and to a “bounds” comparator circuit. The method of using this scheme or comparator circuit allows a quick and easy test to characterize, utilizing a single floating-point bounds comparison function, the location of a point with respect to pre-defined end- points. The single floating-point bounds comparison function represents an additional instruction to be incorporated within computer instruction set architectures when performing trivial acceptance testing during the generation of three-dimensional images or graphics.
摘要翻译：本发明涉及使用“边界”比较器方案和“边界”比较器电路的方法。使用该方案或比较器电路的方法允许使用单个浮点边界比较函数来表征相对于预定义端点的点的位置的快速和容易的测试。单个浮点边界比较函数表示在三维图像或图形的生成期间执行微不足道的验收测试时要结合在计算机指令集架构中的附加指令。

15. 发明授权

US06282628B1 Method and system for a result code for a single-instruction multiple-data predicate compare operation 有权
标题翻译：用于单指令多数据谓词比较操作的结果代码的方法和系统
公开(公告)号：US06282628B1
公开(公告)日：2001-08-28
申请号：US09256374
申请日：1999-02-24
申请人： Pradeep Kumar Dubey , Brett Olsson , Ronald Ray Hochsprung , Hunter Ledbetter Scales, III , Keith Everett Diefendorff
发明人： Pradeep Kumar Dubey , Brett Olsson , Ronald Ray Hochsprung , Hunter Ledbetter Scales, III , Keith Everett Diefendorff
IPC分类号： G06F1580
CPC分类号： G06F9/30021 , G06F9/30036 , G06F9/30072
摘要： A method and system is disclosed which summarizes the results of a classical single-instruction multiple-data SIMD predicate comparison operation, signaling whether all comparisons resulted in a false result or true result, and placing that status into a separate status register, such as the Power PC Condition Register. The method and system utilizes first and second status bits to support the signaling whether all element comparisons resulted in true or false. The first status bit is set when all element comparisons resulted in false (i.e. a NOR of all predicate comparison results), and the second status bit is set when all element comparisons resulted in true (i.e. an AND of all predicate comparison results). This capability allows control flow using conditional branching on the event when all comparison results are false or when all comparison results are true. The method and system of the present invention is useful in 3-D graphics such as lighting and trivial acceptance testing where executing down both paths of a branch and then selecting the correct result is not tolerable.
摘要翻译：公开了一种方法和系统，其总结了经典单指令多数据SIMD谓词比较操作的结果，指示所有比较是否导致错误结果或真实结果，并将该状态置于单独的状态寄存器中，例如电源条件寄存器。该方法和系统利用第一和第二状态位来支持信号是否所有元素比较导致真或假。当所有元素比较导致假（即所有谓词比较结果的NOR）时，第一个状态位被置位，当所有元素比较结果为真时（即所有谓词比较结果的AND），第二个状态位被置位。当所有比较结果为false或所有比较结果为真时，此功能允许使用事件上的条件分支进行控制流程。本发明的方法和系统在诸如照明和平凡验收测试的三维图形中是有用的，其中执行分支的两个路径，然后选择正确的结果是不允许的。

16. 发明授权

US5996057A Data processing system and method of permutation with replication within a vector register file 失效
标题翻译：数据处理系统和在向量寄存器文件中复制的排列方法
公开(公告)号：US5996057A
公开(公告)日：1999-11-30
申请号：US62100
申请日：1998-04-17
申请人： Hunter Ledbetter Scales, III , Keith Everett Diefendorff , Brett Olsson , Pradeep Kumar Dubey , Ronald Ray Hochsprung
发明人： Hunter Ledbetter Scales, III , Keith Everett Diefendorff , Brett Olsson , Pradeep Kumar Dubey , Ronald Ray Hochsprung
IPC分类号： G06F9/30 , G06F9/312 , G06F9/315 , G06F15/78 , G06F9/305 , G06F9/34
CPC分类号： G06F9/30043 , G06F15/8084 , G06F9/30032 , G06F9/30036 , G06F9/30101 , G06F9/3816
摘要： The data processing system of the present invention loads three input operands, including two input vectors and a control vector, into vector registers and performs a permutation of the two input vectors as specified by the control vector, and further stores the result of the operation as the output operand in an output register. The control vector consists of sixteen indices, each uniquely identifying a single byte of input data in either of the input registers, and can be specified in the operational code or be the result of a computation previously performed within the vector registers. The specification of the control vector allows a vector-matrix operation to be performed on the input vectors by rearranging or replicating the input operand bytes in the bytes of the output register as a function of the control vector. This system provides a highly efficient register loading mechanism for data vectors misaligned in memory, and allows the computation of a serially dependent chain of binary functions within the vector registers.
摘要翻译：本发明的数据处理系统将包括两个输入向量和控制向量的三个输入操作数加载到向量寄存器中，并且执行由控制向量指定的两个输入向量的置换，并且将该操作的结果存储为输出寄存器中的输出操作数。控制向量包括十六个索引，每个索引唯一地标识输入寄存器中的任一个输入数据的单个字节，并且可以在操作代码中指定，或者是先前在向量寄存器内执行的计算的结果。控制向量的规范允许通过根据控制向量重新排列或复制输出寄存器的字节中的输入操作数字节来对输入向量执行向量矩阵运算。该系统为存储器中不对齐的数据矢量提供了高效的寄存器加载机制，并允许在向量寄存器内计算二进制函数的连续依赖链。

17. 发明授权

US5832533A Method and system for addressing registers in a data processing unit in an indexed addressing mode 失效
标题翻译：用于以索引寻址模式寻址数据处理单元中的寄存器的方法和系统
公开(公告)号：US5832533A
公开(公告)日：1998-11-03
申请号：US687825
申请日：1996-07-26
申请人： Ramesh Chandra Agarwal , Fred G. Gustavson , Mark A. Johnson , Brett Olsson
发明人： Ramesh Chandra Agarwal , Fred G. Gustavson , Mark A. Johnson , Brett Olsson
IPC分类号： G06F9/30 , G06F9/318 , G06F9/355 , G06F12/02 , G06F12/06
CPC分类号： G06F9/355 , G06F9/3013 , G06F9/30138
摘要： In a data processing unit having a plurality of general purpose registers, an instruction is loaded. Such an instruction includes an operation, and at least one operand field, where the operand field specifies one of a plurality of base registers and a displacement value. To calculate a general purpose register address specified by such an operand field, the displacement value is added to a base value stored in a base register that is specified by a portion of the operand field. Finally, the data processing unit addresses a selected one of the general purpose registers, utilizing the calculated general purpose register address, for execution of the specified operation. Thus, the data processing unit is capable of addressing a larger number of general purpose registers than may be directly addressed utilizing a value represented by a limited number of bits within the operand field.
摘要翻译：在具有多个通用寄存器的数据处理单元中，加载指令。这样的指令包括操作和至少一个操作数字段，其中操作数字段指定多个基本寄存器中的一个和位移值。为了计算由这样一个操作数字段指定的通用寄存器地址，位移值被添加到存储在由一部分操作数字段指定的基址寄存器中的基础值。最后，数据处理单元利用所计算的通用寄存器地址来寻址所选择的一个通用寄存器，以执行指定的操作。因此，数据处理单元能够寻址比可以使用由操作数字段内的有限数目的位表示的值直接寻址的更大数量的通用寄存器。

18. 发明申请

US20120297171A1 METHODS FOR GENERATING CODE FOR AN ARCHITECTURE ENCODING AN EXTENDED REGISTER SPECIFICATION 审中-公开
标题翻译：用于生成用于编码扩展寄存器规范的体系结构的代码的方法
公开(公告)号：US20120297171A1
公开(公告)日：2012-11-22
申请号：US13559334
申请日：2012-07-26
申请人： Michael Karl Gschwind , Robert Kevin Montoye , Brett Olsson , John-David Wellman
发明人： Michael Karl Gschwind , Robert Kevin Montoye , Brett Olsson , John-David Wellman
IPC分类号： G06F9/30
CPC分类号： G06F8/447
摘要： There are provided methods and computer program products for generating code for an architecture encoding an extended register specification. A method for generating code for a fixed-width instruction set includes identifying a non-contiguous register specifier. The method further includes generating a fixed-width instruction word that includes the non-contiguous register specifier.
摘要翻译：提供了用于为编码扩展寄存器规范的架构生成代码的方法和计算机程序产品。用于生成固定宽度指令集的代码的方法包括识别不连续的寄存器说明符。该方法还包括生成包括非连续寄存器说明符的固定宽度指令字。

19. 发明申请

US20120265967A1 IMPLEMENTING INSTRUCTION SET ARCHITECTURES WITH NON-CONTIGUOUS REGISTER FILE SPECIFIERS 有权
标题翻译：使用非连续寄存器文件指定器实施指令集结构
公开(公告)号：US20120265967A1
公开(公告)日：2012-10-18
申请号：US13425808
申请日：2012-03-21
申请人： Michael Karl Gschwind , Robert K. Montoye , Brett Olsson , John-David Wellman
发明人： Michael Karl Gschwind , Robert K. Montoye , Brett Olsson , John-David Wellman
IPC分类号： G06F9/30
CPC分类号： G06F9/30185 , G06F9/30032 , G06F9/30036 , G06F9/30105 , G06F9/30138 , G06F9/3016 , G06F9/30181
摘要： There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing an instruction of an instruction set using a non-contiguous register specifier of a non-contiguous register specification. The instruction includes the non-contiguous register specifier.
摘要翻译：提供了用于实现具有非连续寄存器文件说明符的指令集架构的方法和计算机程序产品。一种用于处理指令代码的方法包括使用非连续寄存器规范的非连续寄存器说明符来处理指令集的指令。该指令包括不连续的寄存器说明符。

20. 发明授权

US07836287B2 Reducing the fetch time of target instructions of a predicted taken branch instruction 失效
标题翻译：减少预测的分支指令的目标指令的获取时间
公开(公告)号：US07836287B2
公开(公告)日：2010-11-16
申请号：US12176385
申请日：2008-07-20
申请人： Richard William Doing , Brett Olsson , Kenichi Tsuchiya
发明人： Richard William Doing , Brett Olsson , Kenichi Tsuchiya
IPC分类号： G06F9/00
CPC分类号： G06F9/3804 , G06F9/3844
摘要： A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced.
摘要翻译：一种用于减少预测的分支指令的目标指令的获取时间的方法和处理器。缓冲器中的每个条目（这里称为“分支目标缓冲器”）可以存储预测的分支指令的地址和从预测的分支指令的目标地址开始的指令。当从指令高速缓存中取出指令时，使用获取的指令的特定位来对分支目标缓冲器中的特定条目进行索引。将索引条目中的分支指令的地址与从指令高速缓存获取的指令的地址进行比较。如果有匹配，则从该分支指令的目标地址开始的指令直接在分支指令的后面进行调度。以这种方式，减少预测的分支指令的目标指令的获取时间。

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