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11. 发明授权

US5654648A Output buffer circuit with low power pre-output drive 失效
标题翻译：输出缓冲电路，具有低功率预输出驱动
公开(公告)号：US5654648A
公开(公告)日：1997-08-05
申请号：US399941
申请日：1995-03-06
申请人： Ajit K. Medhekar , Eric Voelkel
发明人： Ajit K. Medhekar , Eric Voelkel
IPC分类号： H03K19/017 , H03K19/094 , H03K17/04 , H03K19/0185
CPC分类号： H03K19/09429 , H03K19/01707
摘要： An output buffer circuit with low power pre-output driving capability uses existing output drivers and includes input inverters with three-state outputs interposed between the input and output stages and a feedback circuit with three-state outputs connected to the output stage. During normal data transmission, the input inverters buffer the incoming complementary data signals driving the pull-up and pull-down transistors in the output stage while the three-state outputs of the feedback circuit are turned off. Upon receiving an active pre-output control signal, the input inverters are disabled, thereby isolating the pull-up and pull-down transistors from the incoming complementary data signals, and the feedback circuit is enabled. The enabled feedback circuit monitors the signal level of the output signal from the output stage. When the output signal is a logic 0, the feedback circuit turns the pull-up and pull-down transistors on and off, respectively, and when the output signal is a logic 1, the feedback circuit turns the pull-up and pull-down transistors off and on, respectively. Once the output signal has reached the desired pre-output signal level intermediate to the normal logic 0 and logic 1 levels, the feedback circuit rams off both the pull-up and pull-down transistors. Accordingly, an output signal at the desired pre-output signal level is provided with no DC power consumption by the output stage.
摘要翻译：具有低功率预输出驱动能力的输出缓冲电路使用现有的输出驱动器，并且包括插入在输入和输出级之间的三态输出的输入反相器和连接到输出级的三态输出的反馈电路。在正常数据传输期间，输入反相器缓冲输入互补数据信号，驱动输出级的上拉和下拉晶体管，同时反馈电路的三态输出被关断。在接收到有效的预输出控制信号时，输入反相器被禁用，从而将上拉和下拉晶体管与输入的互补数据信号隔离开，并且反馈电路被使能。使能的反馈电路监视来自输出级的输出信号的信号电平。当输出信号为逻辑0时，反馈电路分别导通和关断上拉和下拉晶体管，当输出信号为逻辑1时，反馈电路将上拉和下拉晶体管分别断开和接通。一旦输出信号达到了正常逻辑0和逻辑1电平之间的期望的预输出信号电平，反馈电路就会断开上拉和下拉晶体管。因此，在期望的预输出信号电平处的输出信号不被输出级提供直流功率消耗。

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