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11. 发明授权

US5809271A Method and apparatus for changing flow of control in a processor 失效
标题翻译：改变处理器中控制流程的方法和装置
公开(公告)号：US5809271A
公开(公告)日：1998-09-15
申请号：US518563
申请日：1995-08-23
申请人： Robert P. Colwell , Atiq Bajwa , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , David B. Papworth
发明人： Robert P. Colwell , Atiq Bajwa , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , David B. Papworth
IPC分类号： G06F9/32 , G06F9/38 , G06F9/26
CPC分类号： G06F9/3865 , G06F9/322 , G06F9/3844
摘要： A simplified method and apparatus for handling the change of instruction control flow in a microprocessor is provided. Rather than attempting to implement a change in the instruction flow immediately, the processor first recognizes that flow is to be redirected from a predicted instruction flow to a correct instruction flow according to a flow control indicator. The flow control indicator may be attached to instructions flowing down the pipeline or inserted as a separate instruction in the pipeline. The pipeline is cleared of state created by instructions that do not follow the correct instruction flow, i.e., instructions that were erroneously fetched after the instruction causing the change in flow. The change in flow as indicated by the flow control indicator is implemented later in the pipeline.
摘要翻译：提供了一种用于处理微处理器中指令控制流程变化的简化方法和装置。处理器不是试图立即实现指令流程的改变，而是根据流量控制指示符首先识别流程将从预测指令流重定向到正确的指令流。流量控制指示器可以附接到沿着流水线向下流动的指令或作为管道中的单独指令插入。管道被清除由不遵循正确指令流程的指令创建的状态，即在引起流量变化的指令之后被错误地取出的指令。流量控制指示器所示的流量变化在后面的流水线中实现。

12. 发明授权

US5778245A Method and apparatus for dynamic allocation of multiple buffers in a processor 失效
标题翻译：用于在处理器中动态分配多个缓冲器的方法和装置
公开(公告)号：US5778245A
公开(公告)日：1998-07-07
申请号：US204861
申请日：1994-03-01
申请人： David B. Papworth , Andrew F. Glew , Glenn J. Hinton , Robert P. Colwell , Michael A. Fetterman , Shantanu R. Gupta , James S. Griffith
发明人： David B. Papworth , Andrew F. Glew , Glenn J. Hinton , Robert P. Colwell , Michael A. Fetterman , Shantanu R. Gupta , James S. Griffith
IPC分类号： G06F9/38 , G06F9/50 , G06F15/82
CPC分类号： G06F9/5016 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A method and apparatus for dynamically allocating entries of microprocessor resources to particular instructions in an efficient manner to efficiently utilize buffer size and resources. The pipelined and superscalar microprocessor is capable of speculatively executing instructions and also out-of-order processing. Resources within the microprocessor include a store buffer, a load buffer, a reorder buffer and a reservation station. The reorder buffer contains a larger set of physical registers and also contains information related to speculative instructions and the reservation station comprises information related to instructions pending execution. The load buffer is only allocated to load instructions and is valid for an instruction from allocation pipestage to instruction retirement. The store buffer is only allocated to store instructions and is valid for an instruction from allocation to store performance. The reservation station is allocated to most instructions and is valid for an instruction from allocation to instruction dispatch. The reorder buffer is allocated to all instructions and is valid for a given instruction from allocation to retirement. The load buffer, store buffer, and reorder buffer are sequentially allocated while the reservation station is not. Resource allocation is performed dynamically (as needed by the operation) rather than as a full set of resources attached to each operation. Using the above allocation scheme, efficient usage of the microprocessor resources is accomplished.
摘要翻译：一种用于以有效方式动态地将微处理器资源的条目分配给特定指令以有效利用缓冲器大小和资源的方法和装置。流水线和超标量微处理器能够推测性地执行指令并进行无序处理。微处理器内的资源包括存储缓冲器，加载缓冲器，重新排序缓冲器和保留站。重排序缓冲器包含较大的一组物理寄存器，并且还包含与推测指令相关的信息，并且保留站包括与待执行的指令相关的信息。加载缓冲区仅分配给加载指令，对从分配管理到指令退出的指令有效。存储缓冲区仅被分配用于存储指令，并且对于分配的指令有效以存储性能。保留站被分配给大多数指令，并且对于从分配到指令分派的指令是有效的。重新排序缓冲区被分配给所有指令，并且对于从分配到退休的给定指令是有效的。在保留站不存在的情况下顺序地分配负载缓冲器，存储缓冲器和重排序缓冲器。动态执行资源分配（根据操作需要），而不是作为每个操作附加的一整套资源。使用上述分配方案，可以实现微处理器资源的高效利用。

13. 发明授权

US5584038A Entry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversed 失效
标题翻译：使用指示循环缓冲区的队列是否已遍历的换行符，循环缓冲区中的条目分配
公开(公告)号：US5584038A
公开(公告)日：1996-12-10
申请号：US633905
申请日：1996-04-17
申请人： David B. Papworth , Andrew F. Glew , Michael A. Fetterman , Glenn J. Hinton , Robert P. Colwell , Steven J. Griffith , Shantanu R. Gupta , Narayan Hegde
发明人： David B. Papworth , Andrew F. Glew , Michael A. Fetterman , Glenn J. Hinton , Robert P. Colwell , Steven J. Griffith , Shantanu R. Gupta , Narayan Hegde
IPC分类号： G06F5/10 , G06F5/14 , G06F9/38 , G06F12/00
CPC分类号： G06F5/14 , G06F9/3836 , G06F9/384 , G06F9/3844 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch anti speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries. The allocator utilizes an all or nothing allocation policy, such that either all or no incoming instructions are allocated during an allocation period.
摘要翻译：分配器为循环缓冲区分配条目。分配器接收在循环缓冲器的条目中存储数据的请求，并且生成头指针以标识不分配循环缓冲器条目的循环缓冲器中的起始条目。除了指向循环缓冲区中的条目之外，头指针还包括一个换行位。每次分配器遍历循环缓冲区的线性队列时，分配器将切换换行。生成尾指针，包括换行位，以标识分配循环缓冲区条目的循环缓冲区中的结尾条目。响应于条目请求，分配器顺序分配位于头部指针和尾部指针之间的请求的条目。分配器具有用于执行无序调度的推测执行的微处理器的应用程序。分配器被耦合到配置为循环缓冲器的重排序缓冲器，以允许分配条目。分配器利用全部或全部分配策略，使得在分配周期期间分配全部或者没有传入指令。

14. 发明授权

US5561814A Methods and apparatus for determining memory operating characteristics for given memory locations via assigned address ranges 失效
标题翻译：用于通过分配的地址范围确定给定存储器位置的存储器操作特性的方法和装置
公开(公告)号：US5561814A
公开(公告)日：1996-10-01
申请号：US171528
申请日：1993-12-22
申请人： Andrew F. Glew , Glenn J. Hinton , David B. Papworth , Michael A. Fetterman , Robert P. Colwell , Frederick J. Pollack
发明人： Andrew F. Glew , Glenn J. Hinton , David B. Papworth , Michael A. Fetterman , Robert P. Colwell , Frederick J. Pollack
IPC分类号： G06F12/08 , G06F12/10 , G06F13/10
CPC分类号： G06F12/0888 , G06F12/1027 , G06F2212/206
摘要： A circuit comprising a number of address range registers and complimentary decoding/matching circuits is provided to a processor for determining the memory type of a physical address, thereby allowing memory type to be determined as soon as the physical address is available in an execution stage preceding cache access. Additionally, a memory type field is provided to each address translation lookaside buffer entry of the data and instruction memory subsystem for storing the determined memory type. The memory type determination circuit is disposed in the page miss handler, thereby allowing memory type to be determined at the same time when the physical address is determined.
摘要翻译：包括多个地址范围寄存器和互补解码/匹配电路的电路被提供给处理器，用于确定物理地址的存储器类型，由此一旦物理地址在执行阶段中可用，就允许确定存储器类型缓存访问。此外，存储器类型字段被提供给用于存储确定的存储器类型的数据和指令存储器子系统的每个地址转换后备缓冲器入口。存储器类型确定电路设置在页面未命中处理器中，从而允许在确定物理地址的同时确定存储器类型。

15. 发明授权

US6079014A Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state 失效
标题翻译：检测到错误预测的分支时立即重定向指令提取管道的处理器，同时将事先的指令提交到架构状态
公开(公告)号：US6079014A
公开(公告)日：2000-06-20
申请号：US921852
申请日：1997-09-02
申请人： David B. Papworth , Michael A. Fetterman , Andrew F. Glew , Robert P. Colwell , Glenn J. Hinton
发明人： David B. Papworth , Michael A. Fetterman , Andrew F. Glew , Robert P. Colwell , Glenn J. Hinton
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3806 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3861
摘要： A processor is disclosed comprising a front end circuit that fetches a series of instructions according to a program sequence determined by at least one branch prediction, a register renaming circuit that allocates execution resources to each instruction, and an execution circuit that executes each instruction in the instruction stream. The execution circuit causes the front end circuit to refetch the series of instructions if a branch misprediction is detected. A stall signal disables the register renaming circuit until the execution circuit commits the branch result to an architectural state according to the program sequence.
摘要翻译：公开了一种处理器，其包括前端电路，其根据由至少一个分支预测确定的程序序列取出一系列指令，向每条指令分配执行资源的寄存器重命名电路，以及执行电路，指令流。如果检测到分支错误预测，则执行电路使得前端电路重新提取一系列指令。停止信号禁止寄存器重命名电路，直到执行电路根据程序顺序将分支结果提交到架构状态。

16. 发明授权

US5974523A Mechanism for efficiently overlapping multiple operand types in a microprocessor 失效
标题翻译：在微处理器中有效重叠多个操作数类型的机制
公开(公告)号：US5974523A
公开(公告)日：1999-10-26
申请号：US709216
申请日：1996-09-06
申请人： Andrew F. Glew , Darrell D. Boggs , Michael A. Fetterman , Glenn J. Hinton , Robert P. Colwell , David B. Papworth
发明人： Andrew F. Glew , Darrell D. Boggs , Michael A. Fetterman , Glenn J. Hinton , Robert P. Colwell , David B. Papworth
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/384 , G06F9/30145 , G06F9/30167 , G06F9/3824 , G06F9/3836 , G06F9/3857 , G06F9/3875 , G06F9/3885 , G06F9/3889 , G06F9/3891
摘要： A mechanism for efficiently overlapping multiple operand types is used in a microprocessor which includes a plurality of execution units and a mechanism to provide operations, which include one or more operands, to the plurality of execution units. Each of the plurality of execution units interprets the one or more operands as different types of operands, and the mechanism to provide operations overlaps the different types of operands.
摘要翻译：一种用于有效地重叠多个操作数类型的机制被用于包括多个执行单元的微处理器和一个向多个执行单元提供包括一个或多个操作数的操作的机制。多个执行单元中的每一个将一个或多个操作数解释为不同类型的操作数，并且提供操作的机制与不同类型的操作数重叠。

17. 发明授权

US5729728A Method and apparatus for predicting, clearing and redirecting unpredicted changes in instruction flow in a microprocessor 失效
标题翻译：用于在微处理器中预测，清除和重定向指令流中的未预测变化的方法和装置
公开(公告)号：US5729728A
公开(公告)日：1998-03-17
申请号：US706684
申请日：1996-09-06
申请人： Robert P. Colwell , Atiq Bajwa , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , David B. Papworth
发明人： Robert P. Colwell , Atiq Bajwa , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , David B. Papworth
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/3865 , G06F9/322 , G06F9/3844
摘要： A simplified method and apparatus for handling the change of instruction control flow in a microprocessor is provided. Rather than attempting to implement a change in the instruction flow immediately, the processor first recognizes that flow is to be redirected from a predicted instruction flow to a correct instruction flow according to a flow control indicator. The flow control indicator may be attached to instructions flowing down the pipeline or inserted as a separate instruction in the pipeline. The pipeline is cleared of state created by instructions that do not follow the correct instruction flow, i.e., instructions that were erroneously fetched after the instruction causing the change in flow. The change in flow as indicated by the flow control indicator is implemented later in the pipeline.
摘要翻译：提供了一种用于处理微处理器中指令控制流程变化的简化方法和装置。处理器不是试图立即实现指令流程的改变，而是根据流量控制指示符首先识别流程将从预测指令流重定向到正确的指令流。流量控制指示器可以附接到沿着流水线向下流动的指令或作为管道中的单独指令插入。管道被清除由不遵循正确指令流程的指令创建的状态，即在引起流量变化的指令之后被错误地取出的指令。流量控制指示器所示的流量变化在后面的流水线中实现。

18. 发明授权

US5721855A Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer 失效
标题翻译：通过使用重排序缓冲区之外的寄存器文件来控制对重排序缓冲器的访问的流水线处理指令的方法
公开(公告)号：US5721855A
公开(公告)日：1998-02-24
申请号：US679182
申请日：1996-07-12
申请人： Glenn J. Hinton , David B. Papworth , Andrew F. Glew , Michael A. Fetterman , Robert P. Colwell
发明人： Glenn J. Hinton , David B. Papworth , Andrew F. Glew , Michael A. Fetterman , Robert P. Colwell
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F12/08 , G09F13/04
CPC分类号： G06F9/3867 , G06F12/0855 , G06F9/30054 , G06F9/30058 , G06F9/30152 , G06F9/322 , G06F9/3806 , G06F9/3812 , G06F9/3816 , G06F9/3822 , G06F9/383 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3848 , G06F9/3855 , G06F9/3857 , G06F9/3877 , G06F9/3885 , G06F9/3891 , G09F2013/0472
摘要： A pipelined method for executing instructions in a computer system. The present invention includes providing multiple instructions as a continuous stream of operations. This stream of operations is provided in program order. In one embodiment, the stream of operations is provided by performing an instruction cache memory lookup to fetch the multiple instructions, performing instruction length decoding on the instructions, rotating the instructions, and decoding the instructions. The present invention also performs register renaming, allocates resources and sends a portion of each of the operations to a buffering mechanism (e.g., a reservation station). The instruction cache memory lookup, instruction length decoding, rotation and decoding of the instructions, as well as the register renaming, are performed in consecutive pipestages. The present invention provides for executing the instructions in an out-of-order pipeline. The execution produces results. In one embodiment, the instructions are executed by determining the data readiness of each of the operations and scheduling data ready operations. These scheduled data ready operations are dispatched to an execution unit and executed. The results are written back for use by other operations or as data output or indication. The determination of execution readiness, the dispatching and the execution, and writeback, are performed in consecutive pipestages. The present invention also provides for retiring each of the continuous stream of operations in such a manner as to commit their results to architectural state and to reestablish sequential program order.
摘要翻译：一种用于在计算机系统中执行指令的流水线方法。本发明包括提供多个指令作为连续的操作流。该流程以程序顺序提供。在一个实施例中，通过执行指令高速缓存存储器查找来提取多个指令，对指令执行指令长度解码，旋转指令和解码指令来提供操作流。本发明还执行寄存器重命名，分配资源并将每个操作的一部分发送到缓冲机制（例如，保留站）。在连续的管道中执行指令高速缓存存储器查找，指令长度解码，指令的旋转和解码以及寄存器重命名。本发明提供了在乱序流水线中执行指令。执行产生结果。在一个实施例中，通过确定每个操作的数据准备和调度数据就绪操作来执行指令。这些计划的数据就绪操作被分派到执行单元并被执行。结果被写回以供其他操作使用或作为数据输出或指示。执行准备，调度和执行以及回写的确定是在连续的分支中进行的。本发明还提供以使得其结果落实到架构状态并重新建立顺序程序顺序的方式停止每个连续的操作流。

19. 发明授权

US5615385A Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming 失效
标题翻译：用于零扩展和位移的方法和装置，以在使用寄存器重命名的微处理器中保留寄存器参数
公开(公告)号：US5615385A
公开(公告)日：1997-03-25
申请号：US565646
申请日：1995-11-29
申请人： Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , David B. Papworth , Robert P. Colwell
发明人： Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , David B. Papworth , Robert P. Colwell
IPC分类号： C23C14/35 , C23C16/511 , G06F9/38 , G06F7/00
CPC分类号： G06F9/3885 , G06F9/30036 , G06F9/3824 , G06F9/3826 , G06F9/384 , G06F9/3842
摘要： Register identification preservation in a microprocessor implementing register renaming. Multiplexing and control circuitry are implemented for manipulating data sources to be supplied to a microprocessor's functional units. The circuitry will generate zero extending for source data to an execution unit where a data source register specified is shorter than a general register size utilized by the microprocessor. Similarly, the multiplexing and control circuitry will shift bits of data from one location to another upon a source input to a functional unit in accordance with control signals designating such activity.
摘要翻译：在执行寄存器重命名的微处理器中注册识别保存。实现多路复用和控制电路用于操纵要提供给微处理器功能单元的数据源。电路将产生零延伸用于源数据到执行单元，其中指定的数据源寄存器比微处理器利用的通用寄存器大小短。类似地，根据指定这种活动的控制信号，复用和控制电路将根据源输入到功能单元将数据位从一个位置移位到另一个位置。

20. 发明授权

US5574942A Hybrid execution unit for complex microprocessor 失效
标题翻译：用于复杂微处理器的混合执行单元
公开(公告)号：US5574942A
公开(公告)日：1996-11-12
申请号：US602254
申请日：1996-02-15
申请人： Robert P. Colwell , David B. Papworth , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , Stephen M. Coward , Grace C. Chen
发明人： Robert P. Colwell , David B. Papworth , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , Stephen M. Coward , Grace C. Chen
IPC分类号： G06F9/302 , G06F9/38 , G06F9/30
CPC分类号： G06F9/30014 , G06F9/3885
摘要： A hybrid execution unit for executing miscellaneous instructions in a single clock cycle. The execution unit receives either integer or floating point data, and performs manipulations of two incoming sources to produce a result source in conjunction with existing integer and floating point execution units.
摘要翻译：一种混合执行单元，用于在单个时钟周期内执行各种指令。执行单元接收整数或浮点数据，并执行两个输入源的操作以产生结合现有整数和浮点执行单元的结果源。

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