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11. 发明申请

US20080272814A1 PARALLEL MULTIPLEXING DUTY CYCLE ADJUSTMENT CIRCUIT WITH PROGRAMMABLE RANGE CONTROL 有权
标题翻译：具有可编程范围控制的并行多路复用占空比调整电路
公开(公告)号：US20080272814A1
公开(公告)日：2008-11-06
申请号：US11742845
申请日：2007-05-01
申请人： Meei-Ling Chiang , Sanjeev Maheshwari , Emerson S. Fang
发明人： Meei-Ling Chiang , Sanjeev Maheshwari , Emerson S. Fang
IPC分类号： H03K3/017
CPC分类号： H03K3/017
摘要： A receive interface circuit includes a duty cycle adjustment circuit that adjusts the duty cycle of a reference clock signal based, at least in part, on a selected number of duty cycle adjustment units and a selected range of duty cycle adjustment. The duty cycle adjustment circuit may select as the reference clock signal one of a clock signal and at least a lower version of the clock signal in parallel with the duty cycle adjustment.
摘要翻译：接收接口电路包括占空比调整电路，其至少部分地基于选定数量的占空比调整单元和所选择的占空比调整范围来调整参考时钟信号的占空比。占空比调整电路可以与占空比调整并行地选择时钟信号和至少较低版本的时钟信号之一作为参考时钟信号。

12. 发明授权

US06359579B1 Digital logic correction circuit for a pipeline analog to digital (A/D) converter 有权
标题翻译：用于管线模数（A / D）转换器的数字逻辑校正电路
公开(公告)号：US06359579B1
公开(公告)日：2002-03-19
申请号：US09506037
申请日：2000-02-17
申请人： Meei-Ling Chiang
发明人： Meei-Ling Chiang
IPC分类号： H03M112
CPC分类号： H03M1/0695 , H03M1/0624 , H03M1/442
摘要： A digital logic correction (DLC) circuit for a pipeline analog to digital (A/D) converter. The A/D converter having a plurality of stages, each stage producing at least a pair of digital output bits from which a digital representation of an analog input signal can be obtained. The DLC circuit has an adder, the adder having a plurality of inputs and an output. The DLC circuit has a plurality of digital delay sets, each digital delay set comprising at least one digital delay, an input of the digital delay set receiving a corresponding digital output bit and an output of the delay set providing a delayed digital output bit to a respective adder input. The DLC circuit has a clock generator, the clock generator providing clock signals to the DLC circuit to synchronize the arrival of the output of each digital delay set at the adder inputs during a data-valid-period. A primary clock signal is applied to the digital delay sets for every other stage. A secondary clock signal is applied to the remaining digital delay sets. The timing of the primary and secondary clock signals being effective to delay the digital output bits of each stage via the respective digital delay sets to cause the digital output bits to arrive at the adder inputs during the data-valid-period so that the adder produces the digital representation of the analog input signal at the adder output.
摘要翻译：一种用于流水线模数（A / D）转换器的数字逻辑校正（DLC）电路。具有多级的A / D转换器，每级产生至少一对数字输出位，可从该数字输出位获得模拟输入信号的数字表示。 DLC电路具有加法器，加法器具有多个输入和输出。 DLC电路具有多个数字延迟集合，每个数字延迟组合包括至少一个数字延迟，接收相应数字输出位的数字延迟组的输入和提供延迟的数字输出位的延迟组的输出到各加法器输入。 DLC电路具有时钟发生器，时钟发生器向DLC电路提供时钟信号，以在数据有效期期间使加法器输入处的每个数字延迟设置的输出的到达同步。主时钟信号被应用于每隔一个阶段的数字延迟组。辅助时钟信号被施加到剩余的数字延迟组。主时钟信号和辅助时钟信号的定时有效地通过相应的数字延迟组件来延迟每一级的数字输出位，以在数据有效期间使数字输出位到达加法器输入端，使加法器产生加法器输出端的模拟输入信号的数字表示。

13. 发明授权

US08134417B2 Automatic amplitude control for voltage controlled oscillator 有权
标题翻译：压控振荡器的自动幅度控制
公开(公告)号：US08134417B2
公开(公告)日：2012-03-13
申请号：US12813071
申请日：2010-06-10
申请人： Meei-Ling Chiang , Dennis M. Fischette , Alvin Leng Sun Loke , Michael M. Oshima
发明人： Meei-Ling Chiang , Dennis M. Fischette , Alvin Leng Sun Loke , Michael M. Oshima
IPC分类号： H03B5/12 , H03L5/00
CPC分类号： H03L5/00 , H03L7/099 , H03L7/10
摘要： A circuit and method for calibrating a VCO (voltage controlled oscillator) is disclosed. In one embodiment, a circuit includes a VCO and a bias control circuit coupled to a tail node of the VCO. An amplitude control unit may also be coupled to the tail node, wherein the amplitude control unit is configured to determine the amplitude of a VCO output signal based on a voltage present on the tail node. The amplitude control unit may also be configured to generate a bias voltage based on the amplitude of the VCO output signal and a target voltage. The bias control circuit may be coupled to receive the bias voltage from the amplitude control unit and may be further configured to adjust the voltage on the tail node based on the received bias voltage.
摘要翻译：公开了一种用于校准VCO（压控振荡器）的电路和方法。在一个实施例中，电路包括耦合到VCO的尾部节点的VCO和偏置控制电路。幅度控制单元还可以耦合到尾部节点，其中，幅度控制单元被配置为基于存在于尾部节点上的电压来确定VCO输出信号的幅度。幅度控制单元还可以被配置为基于VCO输出信号的幅度和目标电压来产生偏置电压。偏置控制电路可以被耦合以从幅度控制单元接收偏置电压，并且还可以被配置为基于所接收的偏置电压来调整尾部节点上的电压。

14. 发明申请

US20080297216A1 TEST TECHNIQUES FOR A DELAY-LOCKED LOOP RECEIVER INTERFACE 有权
标题翻译：延迟环路接收机接口的测试技术
公开(公告)号：US20080297216A1
公开(公告)日：2008-12-04
申请号：US11756674
申请日：2007-06-01
申请人： Meei-Ling Chiang , Dwight K. Elvey , Sanjeev Maheshwari , Emerson S. Fang
发明人： Meei-Ling Chiang , Dwight K. Elvey , Sanjeev Maheshwari , Emerson S. Fang
IPC分类号： H03L7/06 , G01R31/28
CPC分类号： G01R31/3016 , G01R31/31725 , H03L7/07 , H03L7/0814 , H03L7/091
摘要： An integrated circuit includes a variable delay circuit configured to generate at least one delayed clock signal based on a first clock signal and a first control signal. The integrated circuit includes a control circuit configured to generate a count value based on a second input signal and a second control signal. The first clock signal is a first version of the at least one delayed clock signal. At least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of a frequency characteristic of the at least one delayed clock signal. The integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal.
摘要翻译：集成电路包括可变延迟电路，其被配置为基于第一时钟信号和第一控制信号产生至少一个延迟的时钟信号。集成电路包括配置为基于第二输入信号和第二控制信号产生计数值的控制电路。第一时钟信号是至少一个延迟时钟信号的第一版本。所述第二输入信号和所述第二控制信号中的至少一个是所述至少一个延迟时钟信号的第二版本，并且所述计数值指示所述至少一个延迟的时钟信号的频率特性。集成电路被配置为在一个值的范围内单调地改变第一控制信号，并且针对控制信号的各个值确定计数值。

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