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11. 发明授权

US07696607B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07696607B2
公开(公告)日：2010-04-13
申请号：US11889210
申请日：2007-08-09
申请人： Hikari Sano , Masao Takahashi , Hiroshige Hirano , Koji Takemura
发明人： Hikari Sano , Masao Takahashi , Hiroshige Hirano , Koji Takemura
IPC分类号： H01L23/544
CPC分类号： H01L23/585 , H01L21/78 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a circuit region having a function element formed on a semiconductor substrate; a scribe region located between the circuit region and another circuit region formed spaced from the circuit region, the scribe region including a cutting region and non-cutting regions provided at both sides of the cutting region; a first interlayer insulating film formed in the scribe region on the semiconductor substrate; a first dummy pattern made of conductive material and formed in the first interlayer insulating film in the cutting region; and a second dummy pattern made of conductive material and formed in the first interlayer insulating film in each of the non-cutting regions. The ratio, per unit area, of the area of the first dummy pattern to the area of the cutting region is lower than the ratio, per unit area, of the area of the second dummy pattern to the area of the non-cutting regions.
摘要翻译：半导体器件包括：具有形成在半导体衬底上的功能元件的电路区域; 位于所述电路区域和与所述电路区域间隔开的另一电路区域之间的划线区域，所述划线区域包括切割区域和设置在所述切割区域两侧的非切割区域; 形成在半导体衬底上的划线区域中的第一层间绝缘膜; 由导电材料制成并形成在切割区域中的第一层间绝缘膜中的第一虚设图形; 以及由导电材料制成并形成在每个非切割区域中的第一层间绝缘膜中的第二虚设图案。第一虚设图形的面积与切割区域的面积的单位面积的比率低于第二虚拟图案的面积与非切割区域的面积的每单位面积的比率。

12. 发明授权

US07888801B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07888801B2
公开(公告)日：2011-02-15
申请号：US12430439
申请日：2009-04-27
申请人： Koji Takemura , Hiroshige Hirano , Yutaka Itoh , Hikari Sano , Masao Takahashi , Koji Koike
发明人： Koji Takemura , Hiroshige Hirano , Yutaka Itoh , Hikari Sano , Masao Takahashi , Koji Koike
IPC分类号： H01L23/522
CPC分类号： H01L23/585 , H01L21/76832 , H01L23/522 , H01L23/53295 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.
摘要翻译：一种半导体器件包括在半导体衬底上的层间绝缘膜中堆叠的至少三个或更多个布线层，设置在半导体衬底的芯片区域的外周处的密封环和在芯片区域的一部分中提供的芯片强度增强靠近密封圈。芯片强度加强件由多个虚拟布线结构构成，并且多个虚设布线结构中的每一个形成为跨越两个或更多个布线层中的两个或更多个布线层，包括最下面的布线层和最上面的布线层使用通孔部分。

13. 发明授权

US08456024B2 Semiconductor device having a pad-disposition restriction area 有权
标题翻译：具有垫配置限制区域的半导体器件
公开(公告)号：US08456024B2
公开(公告)日：2013-06-04
申请号：US13489215
申请日：2012-06-05
申请人： Manabu Ohnishi , Koji Takemura , Noriyuki Nagai , Hoyeun Huh , Tomoyuki Nakayama , Atsushi Doi
发明人： Manabu Ohnishi , Koji Takemura , Noriyuki Nagai , Hoyeun Huh , Tomoyuki Nakayama , Atsushi Doi
IPC分类号： H01L23/52
CPC分类号： H01L24/06 , H01L23/3114 , H01L23/50 , H01L2224/0401 , H01L2224/05552 , H01L2224/05555 , H01L2224/06153 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/3011 , H01L2924/00012
摘要： Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.
摘要翻译：形成输入/输出单元以便在半导体芯片的表面上与角单元相邻地周边布置，并且在相应的输入/输出单元上形成电极焊盘。电极焊盘被配置成Z字形排列，以形成内部和外部焊盘阵列。然而，在形成内焊盘阵列的电极焊盘中，与角电池两侧相邻的预定区域中的那些电极焊盘没有布置，使得凸起接合到半导体芯片的载体的互连图案和通孔被阻止变得复杂。

14. 发明申请

US20130038738A1 RADIATION IMAGE CAPTURING SYSTEM 有权
标题翻译：辐射图像捕获系统
公开(公告)号：US20130038738A1
公开(公告)日：2013-02-14
申请号：US13643589
申请日：2011-02-25
申请人： Takanori Ando , Chikako Tokuno , Koji Takemura , Akira Kurahashi
发明人： Takanori Ando , Chikako Tokuno , Koji Takemura , Akira Kurahashi
IPC分类号： H04N5/30
CPC分类号： G03B42/02 , A61B6/4233 , A61B6/4266 , A61B6/4283 , A61B6/4291 , A61B6/4405 , A61B6/4494 , A61B6/463 , A61B6/464 , A61B6/465 , A61B6/488 , A61B6/5294 , A61B6/542 , A61B6/545 , A61B6/548 , A61B6/563 , A61B6/585 , A61B6/587 , G03B42/025 , G03B42/04 , G06F19/00 , G06F19/3481
摘要： According to one implementation of the present invention, there is provided a radiation image capturing system. The system includes, a radiation source; a plurality of radiation image capturing devices; and a console. The console manages which of the radiation image capturing devices is in a state where image capturing is possible. The console registers image capturing order information including information of which radiation image capturing device is used in the image capturing, or obtains the registered image capturing order information. When there is a radiation image capturing device in a state where image capturing is possible, regardless of a predetermined order, the console displays the icon corresponding to the image capturing order information including information of the radiation image capturing device in a manner different from the other icons.
摘要翻译：根据本发明的一个实施方式，提供了一种放射线图像捕获系统。该系统包括：辐射源; 多个放射线图像捕获装置; 和一个控制台。控制台管理哪个辐射图像捕获装置处于可能进行图像拍摄的状态。控制台登记图像拍摄顺序信息，包括在图像拍摄中使用哪个放射线图像拍摄装置的信息，或者获得登记图像拍摄顺序信息。当存在可以进行图像拍摄的状态下的放射线图像捕获装置时，无论预定顺序如何，控制台以与其他方式不同的方式显示与包括放射线图像捕获装置的信息的图像拍摄顺序信息相对应的图标图标。

15. 发明申请

US20120306915A1 DISPLAY DEVICE, METHOD OF CONTROLLING DISPLAY DEVICE, AND RECORDING MEDIUM 审中-公开
标题翻译：显示装置，控制显示装置的方法和记录介质
公开(公告)号：US20120306915A1
公开(公告)日：2012-12-06
申请号：US13483334
申请日：2012-05-30
申请人： Koji Takemura
发明人： Koji Takemura
IPC分类号： G09G5/377
CPC分类号： G06F3/1454 , G09G5/14 , G09G5/373 , G09G5/377 , G09G5/397
摘要： A display device adapted to display an input image includes a display section adapted to display the input image, a designation section adapted to designate a holding area in a first input image displayed by the display section, an image storage section adapted to store a whole of the first input image presently displayed in response to designation of the holding area of the first input image by the designation section, a superimposition processing unit adapted to extract the holding area designated by the designation section from the first input image stored in the image storage section, and then superimpose the extracted holding area to a second input image input after inputting the first input image to thereby generate a superimposed image, and a display control section adapted to make the display section display the superimposed image generated by the superimposition processing unit.
摘要翻译：适于显示输入图像的显示装置包括适于显示输入图像的显示部分，适于指定由显示部分显示的第一输入图像中的保持区域的指定部分，适于存储整体的图像存储部分响应于由指定部分指定第一输入图像的保持区域而当前显示的第一输入图像，适于从存储在图像存储部分中的第一输入图像中提取由指定部分指定的保持区域的叠加处理单元，然后将所提取的保持区域叠加到输入第一输入图像之后的第二输入图像，从而生成叠加图像;以及显示控制部分，其适于使显示部分显示由叠加处理单元生成的叠加图像。

16. 发明授权

US07847418B2 Semiconductor device 有权
公开(公告)号：US07847418B2
公开(公告)日：2010-12-07
申请号：US12688506
申请日：2010-01-15
申请人： Manabu Ohnishi , Koji Takemura , Noriyuki Nagai , Hoyeun Huh , Tomoyuki Nakayama , Atsushi Doi
发明人： Manabu Ohnishi , Koji Takemura , Noriyuki Nagai , Hoyeun Huh , Tomoyuki Nakayama , Atsushi Doi
IPC分类号： H01L23/48
CPC分类号： H01L24/06 , H01L23/3114 , H01L23/50 , H01L2224/0401 , H01L2224/05552 , H01L2224/05555 , H01L2224/06153 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/3011 , H01L2924/00012
摘要： Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.

17. 发明申请

US20100117083A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100117083A1
公开(公告)日：2010-05-13
申请号：US12688506
申请日：2010-01-15
申请人： Manabu OHNISHI , Koji Takemura , Noriyuki Nagai , Hoyeun Huh , Tomoyuki Nakayama , Atsushi Doi
发明人： Manabu OHNISHI , Koji Takemura , Noriyuki Nagai , Hoyeun Huh , Tomoyuki Nakayama , Atsushi Doi
IPC分类号： H01L23/48 , H01L23/488
CPC分类号： H01L24/06 , H01L23/3114 , H01L23/50 , H01L2224/0401 , H01L2224/05552 , H01L2224/05555 , H01L2224/06153 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/3011 , H01L2924/00012
摘要： Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.
摘要翻译：形成输入/输出单元以便在半导体芯片的表面上与角单元相邻地周边布置，并且在相应的输入/输出单元上形成电极焊盘。电极焊盘被配置成Z字形排列，以形成内部和外部焊盘阵列。然而，在形成内焊盘阵列的电极焊盘中，与角电池两侧相邻的预定区域中的那些电极焊盘没有布置，使得凸起接合到半导体芯片的载体的互连图案和通孔被阻止变得复杂。

18. 发明申请

US20070096320A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070096320A1
公开(公告)日：2007-05-03
申请号：US11584561
申请日：2006-10-23
申请人： Koji Takemura , Hiroshige Hirano , Yutaka Itoh , Koji Koike
发明人： Koji Takemura , Hiroshige Hirano , Yutaka Itoh , Koji Koike
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L24/05 , H01L2224/05073 , H01L2224/05082 , H01L2224/05093 , H01L2224/05147 , H01L2224/05166 , H01L2224/05187 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/01007 , H01L2924/00014
摘要： A Ti barrier film and a TiN barrier film are formed between a top-level pad made of copper or an alloy film mainly composed of copper and an Al pad. The Ti barrier film is formed to have a greater thickness than the TiN barrier film.
摘要翻译：在由铜构成的顶级焊盘或主要由铜和铝焊盘构成的合金膜之间形成Ti阻挡膜和TiN阻挡膜。 Ti阻挡膜形成为具有比TiN阻挡膜更大的厚度。

19. 发明授权

US08841753B2 Semiconductor device having seal wiring 有权
标题翻译：具有密封接线的半导体器件
公开(公告)号：US08841753B2
公开(公告)日：2014-09-23
申请号：US13428992
申请日：2012-03-23
申请人： Koji Takemura , Hiroshige Hirano , Yutaka Itoh , Hikari Sano , Koji Koike
发明人： Koji Takemura , Hiroshige Hirano , Yutaka Itoh , Hikari Sano , Koji Koike
IPC分类号： H01L23/544
CPC分类号： H01L23/585 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.
摘要翻译：半导体器件包括：形成在衬底上的层间绝缘膜; 在衬底的芯片区域中的层间绝缘膜中形成的布线; 密封环，形成在所述芯片区域的周围的所述层间绝缘膜中，并且连续地围绕所述芯片区域; 以及形成在其上形成有布线和密封环的层间绝缘膜上的第一保护膜。当从芯片区域观察时，在位于密封环外侧的区域中的第一保护膜中形成第一开口，并且层间绝缘膜在第一开口中露出。

20. 发明申请

US20090108410A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090108410A1
公开(公告)日：2009-04-30
申请号：US12137018
申请日：2008-06-11
申请人： Koji Takemura , Takahiro Kumakawa , Yoshihiro Matsushima
发明人： Koji Takemura , Takahiro Kumakawa , Yoshihiro Matsushima
IPC分类号： H01L23/544
CPC分类号： H01L23/585 , H01L21/78 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate, a diffusion layer conductive film formed on the semiconductor substrate, an interlayer insulating film layered on the semiconductor substrate, an interconnect pattern and a via pattern formed in the interlayer insulating film, a plurality of circuit regions formed in the semiconductor substrate, and a scribe region formed around the circuit regions and separating the circuit regions from each other. The diffusion layer conductive film is not formed at least in a region to which laser light is emitted in the scribe region.
摘要翻译：半导体器件包括半导体衬底，形成在半导体衬底上的扩散层导电膜，层叠在半导体衬底上的层间绝缘膜，形成在层间绝缘膜中的布线图案和通孔图案，多个电路区域形成在半导体衬底和形成在电路区域周围并将电路区域彼此分离的划线区域。扩散层导电膜至少在划线区域内不会形成激光的区域。

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