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    • 12. 发明授权
    • Semiconductor device having an improved interlayer conductor connections and a manufacturing method thereof
    • 具有改进的层间导体连接的半导体器件及其制造方法
    • US06727170B2
    • 2004-04-27
    • US09903760
    • 2001-07-13
    • Yoshifumi TakataYuichi SakaiHiroyuki ChibaharaMasanobu Iwasaki
    • Yoshifumi TakataYuichi SakaiHiroyuki ChibaharaMasanobu Iwasaki
    • H01L2100
    • H01L23/5226H01L21/76819H01L21/76838H01L23/5329H01L23/53295H01L2924/0002H01L2924/00
    • There is described a semiconductor device which prevents a short circuit between a wiring layer formed in interlayer insulating films and vertical conductor plugs formed in the vicinity of the wiring layer, and a method of manufacturing the semiconductor device. The semiconductor device includes a first interlayer insulating film smoothly formed on a semiconductor substrate, conductor plugs which are formed by filling openings formed in the first interlayer insulating film so as to be level with the surface of the first interlayer insulating film, a second interlayer insulating film formed on the surface of the first interlayer insulating film and of the conductor plugs, a wiring pattern formed on the second interlayer insulating film, a third interlayer insulating film formed on the surface of the second interlayer insulating film so as to cover the wiring pattern, and an interconnect conductor formed so as to be electrically connected to the conductor plugs by filling the openings penetrating the second and third interlayer insulating films.
    • 描述了防止在层间绝缘膜中形成的布线层和形成在布线层附近的垂直导体插塞之间的短路的半导体器件,以及半导体器件的制造方法。 半导体器件包括在半导体衬底上平滑地形成的第一层间绝缘膜,通过填充形成在第一层间绝缘膜中的开口以与第一层间绝缘膜的表面平齐而形成的导体插塞,第二层间绝缘 形成在第一层间绝缘膜和导体插塞的表面上的膜,形成在第二层间绝缘膜上的布线图案,形成在第二层间绝缘膜的表面上以覆盖布线图案的第三层间绝缘膜 以及互连导体,其通过填充贯穿第二和第三层间绝缘膜的开口而形成为与导体插塞电连接。
    • 16. 发明授权
    • Semiconductor device having an improved interlayer conductor connections and a manufacturing method thereof
    • 具有改进的层间导体连接的半导体器件及其制造方法
    • US06278187B1
    • 2001-08-21
    • US09122650
    • 1998-07-27
    • Yoshifumi TakataYuichi SakaiHiroyuki ChibaharaMasanobu Iwasaki
    • Yoshifumi TakataYuichi SakaiHiroyuki ChibaharaMasanobu Iwasaki
    • H01L2348
    • H01L23/5329H01L21/76819H01L21/76838H01L23/5226H01L23/53295H01L2924/0002H01L2924/00
    • There is described a semiconductor device which prevents a short circuit between a wiring layer formed in interlayer insulating films and vertical conductor plugs formed in the vicinity of the wiring layer, and a method of manufacturing the semiconductor device. The semiconductor device includes a first interlayer insulating film smoothly formed on a semiconductor substrate, conductor plugs which are formed by filling openings formed in the first interlayer insulating film so as to be level with the surface of the first interlayer insulating film, a second interlayer insulating film formed on the surface of the first interlayer insulating film and of the conductor plugs, a wiring pattern formed on the second interlayer insulating film, a third interlayer insulating film formed on the surface of the second interlayer insulating film so as to cover the wiring pattern, and an interconnect conductor formed so as to be electrically connected to the conductor plugs by filling the openings penetrating the second and third interlayer insulating films.
    • 描述了防止在层间绝缘膜中形成的布线层和形成在布线层附近的垂直导体插塞之间的短路的半导体器件,以及半导体器件的制造方法。 半导体器件包括在半导体衬底上平滑地形成的第一层间绝缘膜,通过将形成在第一层间绝缘膜中的开口填充以与第一层间绝缘膜的表面平齐而形成的导体插塞,第二层间绝缘膜 形成在第一层间绝缘膜和导体插塞的表面上的膜,形成在第二层间绝缘膜上的布线图案,形成在第二层间绝缘膜的表面上以覆盖布线图案的第三层间绝缘膜 以及互连导体,其通过填充贯穿第二和第三层间绝缘膜的开口而形成为与导体插塞电连接。