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11. 发明授权

US07995377B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07995377B2
公开(公告)日：2011-08-09
申请号：US12624272
申请日：2009-11-23
申请人： Masanao Yamaoka , Takayuki Kawahara
发明人： Masanao Yamaoka , Takayuki Kawahara
IPC分类号： G11C11/00 , G11C11/34 , G11C5/06 , G11C5/14
CPC分类号： G11C11/412
摘要： An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode.Another object of the present invention is to provide a technique of preventing an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area.Still another object of the present invention is to provide a technique of ensuring stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.
摘要翻译：本发明的目的是提供一种降低使用按比例缩小的晶体管的整个低功耗SRAM LSI电路的功耗的技术，并且通过减少亚阈值泄漏电流来增加对存储单元的读和写操作的稳定性以及从漏极流到基板电极的漏电流。本发明的另一个目的是提供一种防止存储单元中的晶体管数量增加从而防止单元区域增加的技术。本发明的另一个目的是提供一种通过控制驱动晶体管的BOX层下的阱的电位来确保由具有BOX层的SOI或FD-SOI晶体管构成的SRAM存储单元的稳定工作的技术。

12. 发明申请

US20110122681A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110122681A1
公开(公告)日：2011-05-26
申请号：US13021556
申请日：2011-02-04
申请人： Masanao YAMAOKA , Takayuki Kawahara
发明人： Masanao YAMAOKA , Takayuki Kawahara
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode.Another object of the present invention is to provide a technique of preventing an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area.Still another object of the present invention is to provide a technique of ensuring stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.
摘要翻译：本发明的目的是提供一种降低使用按比例缩小的晶体管的整个低功耗SRAM LSI电路的功耗的技术，并且通过减少亚阈值泄漏电流来增加对存储单元的读和写操作的稳定性以及从漏极流到基板电极的漏电流。本发明的另一个目的是提供一种防止存储单元中的晶体管数量增加从而防止单元区域增加的技术。本发明的另一个目的是提供一种通过控制驱动晶体管的BOX层下的阱的电位来确保由具有BOX层的SOI或FD-SOI晶体管构成的SRAM存储单元的稳定工作的技术。

13. 发明授权

US07808045B2 Semiconductor device and semiconductor integrated circuit using the same 失效
标题翻译：半导体器件和半导体集成电路使用相同
公开(公告)号：US07808045B2
公开(公告)日：2010-10-05
申请号：US12767548
申请日：2010-04-26
申请人： Takayuki Kawahara , Masanao Yamaoka
发明人： Takayuki Kawahara , Masanao Yamaoka
IPC分类号： H01L23/62
CPC分类号： H01L27/1203 , H01L29/78645 , H01L29/78648
摘要： The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit.In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.
摘要翻译：本发明提供一种可在宽温度范围内工作的高速，低功耗的LSI，其具有根据电路的工作特性专门使用具有后栅的MOS晶体管。在LSI中，使用具有嵌入的氧化膜层的FD-SOI结构，并且将埋入的氧化膜层的下半导体区域用作后栅。在逻辑电路块中具有小负载的逻辑电路中的后门的电压响应于块外部的激活而被控制。栅极和背栅彼此连接的晶体管用于产生背栅极驱动信号的电路，以及具有诸如电路块输出部分的重负载的逻辑电路，并且后门直接根据到门输入信号。

14. 发明申请

US20080203403A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20080203403A1
公开(公告)日：2008-08-28
申请号：US11960680
申请日：2007-12-19
申请人： Takayuki Kawahara , Masanao Yamaoka , Nobuyuki Sugii
发明人： Takayuki Kawahara , Masanao Yamaoka , Nobuyuki Sugii
IPC分类号： H01L33/00 , H01L27/12
CPC分类号： H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/11526 , H01L27/11546 , H01L27/1203 , H01L27/153
摘要： The semiconductor integrated circuit (1) has a memory (4) and a logic circuit (5), which are mixedly palletized on a silicon substrate (2). The memory includes a partially-depleted type nMOS (6) having an SOI structure and formed on UTB (3). The partially-depleted type nMOS has a backgate region (14) under UTB, to which a voltage can be applied independently of a corresponding gate terminal. The logic circuit includes an nMOS (7) and a pMOS (8), and both are of a fully-depleted type, formed on UTB and have an SOI structure. The fully-depleted type nMOS and pMOS have backgate regions (14, 22) under respective UTBs, to which voltages can be applied independently of the corresponding gate terminals
摘要翻译：半导体集成电路（1）具有在硅衬底（2）上混合堆垛的存储器（4）和逻辑电路（5）。存储器包括具有SOI结构并形成在UTB（3）上的部分耗尽型nMOS（6）。部分耗尽型nMOS在UTB之下具有背栅区域（14），独立于对应的栅极端子可以施加电压。逻辑电路包括nMOS（7）和pMOS（8），并且它们都是完全耗尽型的，形成在UTB上并具有SOI结构。完全耗尽型nMOS和pMOS在相应的UTB下具有背栅区域（14,22），可以独立于对应的栅极端子施加电压

15. 发明申请

US20070246767A1 Semiconductor device formed on a SOI substrate 审中-公开
标题翻译：形成在SOI衬底上的半导体器件
公开(公告)号：US20070246767A1
公开(公告)日：2007-10-25
申请号：US11812694
申请日：2007-06-21
申请人： Kenichi Osada , Takayuki Kawahara , Masanao Yamaoka
发明人： Kenichi Osada , Takayuki Kawahara , Masanao Yamaoka
IPC分类号： H01L29/76
CPC分类号： H01L29/78648 , G11C11/412 , H01L21/823878 , H01L21/84 , H01L27/0928 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L29/4908 , H01L29/78609 , H01L2924/0002 , H01L2924/00
摘要： Thresholds of MISFETS of a Full Depletion-type SOI substrate cannot be controlled by changing impurity density as with bulk silicon MISFETs. Therefore, it is difficult to set a suitable threshold for each circuit. According to the semiconductor device of the present invention, gate electrodes of P-channel type MISFETs composing a memory cell are made of N-type polysilicon, gate electrodes of N-channel type MISFETs are made of P-type polysilicon and gate electrodes of P-channel type and N-channel type MISFETs of peripheral circuits and a logic circuit are made of P-type silicon germanium. A suitable threshold can be achieved for each circuit using a SOI substrate, thereby making it possible to fully leverage the characteristics of the SOI substrate.
摘要翻译：完全耗尽型SOI衬底的MISFETS的阈值不能通过改变杂质密度来控制，就像体硅硅MISFET那样。因此，难以为每个电路设定合适的阈值。根据本发明的半导体器件，构成存储单元的P沟道型MISFET的栅电极由N型多晶硅制成，N沟道型MISFET的栅电极由P型多晶硅制成，栅电极为P 通道型和外围电路的N沟道型MISFET和逻辑电路由P型硅锗制成。对于使用SOI衬底的每个电路，可以实现合适的阈值，从而可以充分利用SOI衬底的特性。

16. 发明授权

US08203868B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08203868B2
公开(公告)日：2012-06-19
申请号：US13021556
申请日：2011-02-04
申请人： Masanao Yamaoka , Takayuki Kawahara
发明人： Masanao Yamaoka , Takayuki Kawahara
IPC分类号： G11C11/00 , G11C5/02 , G11C5/06
CPC分类号： G11C11/412
摘要： An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode.Another object of the present invention is to provide a technique of preventing an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area.Still another object of the present invention is to provide a technique of ensuring stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.
摘要翻译：本发明的目的是提供一种降低使用按比例缩小的晶体管的整个低功耗SRAM LSI电路的功耗的技术，并且通过减少亚阈值泄漏电流来增加对存储单元的读和写操作的稳定性以及从漏极流到基板电极的漏电流。本发明的另一个目的是提供一种防止存储单元中的晶体管数量增加从而防止单元区域增加的技术。本发明的另一个目的是提供一种通过控制驱动晶体管的BOX层下的阱的电位来确保由具有BOX层的SOI或FD-SOI晶体管构成的SRAM存储单元的稳定工作的技术。

17. 发明申请

US20110188329A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20110188329A1
公开(公告)日：2011-08-04
申请号：US13086377
申请日：2011-04-13
申请人： Takayuki Kawahara , Masanao Yamaoka , Nobuyuki Sugii
发明人： Takayuki Kawahara , Masanao Yamaoka , Nobuyuki Sugii
IPC分类号： G11C7/00 , H01L27/088
CPC分类号： H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/11526 , H01L27/11546 , H01L27/1203 , H01L27/153
摘要： The semiconductor integrated circuit (1) has a memory (4) and a logic circuit (5), which are mixedly palletized on a silicon substrate (2). The memory includes a partially-depleted type nMOS (6) having an SOI structure and formed on UTB (3). The partially-depleted type nMOS has a backgate region (14) under UTB, to which a voltage can be applied independently of a corresponding gate terminal. The logic circuit includes an nMOS (7) and a pMOS (8), and both are of a fully-depleted type, formed on UTB and have an SOI structure. The fully-depleted type nMOS and pMOS have backgate regions (14, 22) under respective UTBs, to which voltages can be applied independently of the corresponding gate terminals
摘要翻译：半导体集成电路（1）具有在硅衬底（2）上混合堆垛的存储器（4）和逻辑电路（5）。存储器包括具有SOI结构并形成在UTB（3）上的部分耗尽型nMOS（6）。部分耗尽型nMOS在UTB之下具有背栅区域（14），独立于对应的栅极端子可以施加电压。逻辑电路包括nMOS（7）和pMOS（8），并且它们都是完全耗尽型的，形成在UTB上并具有SOI结构。完全耗尽型nMOS和pMOS在相应的UTB下具有背栅区域（14,22），可以独立于对应的栅极端子施加电压

18. 发明授权

US07943996B2 Semiconductor device and semiconductor integrated circuit using the same 失效
标题翻译：半导体器件和半导体集成电路使用相同
公开(公告)号：US07943996B2
公开(公告)日：2011-05-17
申请号：US12875097
申请日：2010-09-02
申请人： Takayuki Kawahara , Masanao Yamaoka
发明人： Takayuki Kawahara , Masanao Yamaoka
IPC分类号： H01L23/62
CPC分类号： H01L27/1203 , H01L29/78645 , H01L29/78648
摘要： The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit.In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.
摘要翻译：本发明提供一种可在宽温度范围内工作的高速，低功耗的LSI，其具有根据电路的工作特性专门使用具有后栅的MOS晶体管。在LSI中，使用具有嵌入的氧化膜层的FD-SOI结构，并且将埋入的氧化膜层的下半导体区域用作后栅。在逻辑电路块中具有小负载的逻辑电路中的后门的电压响应于块外部的激活而被控制。栅极和背栅彼此连接的晶体管用于产生背栅极驱动信号的电路，以及具有诸如电路块输出部分的重负载的逻辑电路，并且后门直接根据到门输入信号。

19. 发明授权

US07633315B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07633315B2
公开(公告)日：2009-12-15
申请号：US11567774
申请日：2006-12-07
申请人： Masanao Yamaoka , Takayuki Kawahara
发明人： Masanao Yamaoka , Takayuki Kawahara
IPC分类号： H03K17/16 , H03K19/003 , H03K19/094 , H03K3/01 , G05F1/10 , G05F3/02
CPC分类号： H03K19/0016 , G11C11/413
摘要： An object of the present invention is to provide a technique of reducing the leakage current of a drive circuit for driving a circuit that must retain a potential (or information) when in its standby state.A semiconductor integrated circuit device of the present invention includes a drive circuit for driving a circuit block. This drive circuit is made up of a double gate transistor with gates having different gate oxide film thicknesses. When the circuit block is in its standby state, the gate of the double gate transistor having a thinner gate oxide film is turned off and that having a thicker gate oxide film is turned on. This arrangement allows a reduction in the leakage currents of both the circuit block and the drive circuit while allowing the drive circuit to deliver or cut off power to the circuit block.
摘要翻译：本发明的目的是提供一种降低驱动电路的泄漏电流的技术，该驱动电路在处于其待机状态时必须保持电位（或信息）的驱动电路。本发明的半导体集成电路器件包括用于驱动电路块的驱动电路。该驱动电路由具有不同栅极氧化膜厚度的栅极的双栅极晶体管构成。当电路块处于其待机状态时，具有较薄栅极氧化膜的双栅极晶体管的栅极截止，并且具有较厚栅极氧化膜的栅极导通。这种布置允许减少电路块和驱动电路的漏电流，同时允许驱动电路传送或切断电路块的电力。

20. 发明申请

US20090129142A1 SEMICONDUCTOR MEMORY 审中-公开
标题翻译：半导体存储器
公开(公告)号：US20090129142A1
公开(公告)日：2009-05-21
申请号：US12357663
申请日：2009-01-22
申请人： Masanao Yamaoka , Kenichi Osada , Kiyoo Itoh , Takayuki Kawahara
发明人： Masanao Yamaoka , Kenichi Osada , Kiyoo Itoh , Takayuki Kawahara
IPC分类号： G11C11/00 , H01L27/01
CPC分类号： H01L27/11 , G11C11/412 , H01L21/84 , H01L27/108 , H01L27/1203 , Y10S257/903
摘要： A SRAM memory is composed of FD-SOI transistors, and performance of the memory cell is improved by controlling an electric potential of a layer under a buried oxide film of a SOI transistor constituting a driver transistor. Performance of the SRAM circuit in the low power voltage state is improved. In the SRAM memory cell composed of the FD-SOI transistor, an electric potential of a well under a BOX layer is controlled to control a threshold voltage Vth, thereby increasing a current. Thus, the operations of the memory cell can be stabilized.
摘要翻译： SRAM存储器由FD-SOI晶体管组成，通过控制构成驱动晶体管的SOI晶体管的埋入氧化膜下的层的电位来提高存储单元的性能。提高了处于低功率电压状态的SRAM电路的性能。在由FD-SOI晶体管构成的SRAM存储单元中，控制BOX层下的阱的电位来控制阈值电压Vth，从而增加电流。因此，可以稳定存储单元的操作。

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