专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20100070802A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND TESTING METHOD THEREFOR 有权
标题翻译：半导体集成电路及其测试方法
公开(公告)号：US20100070802A1
公开(公告)日：2010-03-18
申请号：US12529458
申请日：2008-02-19
申请人： Hiroaki Inoue , Masamichi Takagi
发明人： Hiroaki Inoue , Masamichi Takagi
IPC分类号： G06F11/273
CPC分类号： G01R31/31724 , G01R31/31723 , G01R31/318536 , G06F11/2236
摘要： A semiconductor integrated circuit comprises a plurality of cores (99) connected with an inter-connection network (1000) and a test controller (500) which is connected with the inter-connection network (1000) and which issues a test control request associated with the test of the core (99) via the inter-connection network (1000). The inter-connection network (1000) is constituted of a plurality of adapters (3000) which serve as connection interfaces of the plurality of cores (99) and the test controller (500), respectively, and a plurality of routers (2000) which connect the plurality of adapters (3000). The adapters (3000) connected with the core (99) comprise a core testing unit for vicariously testing core (99) connected to itself based on the test control request received from the test controller (500) via the inter-connection network (1000).
摘要翻译：半导体集成电路包括与互连网络（1000）连接的多个核（99）和与所述互连网络（1000）连接的测试控制器（500），并且发出与通过互连网络（1000）对核心（99）进行测试。互连网络（1000）由分别用作多个核（99）和测试控制器（500）的连接接口的多个适配器（3000）和多个路由器（2000）组成，多个路由器连接多个适配器（3000）。与核心（99）连接的适配器（3000）包括核心测试单元，用于根据从测试控制器（500）经由互连网络（1000）接收的测试控制请求代替连接到其自身的核心（99）。

12. 发明授权

US08412867B2 Semiconductor integrated circuit and filter and informational delivery method using same 有权
标题翻译：半导体集成电路和滤波器及信息传递方法使用相同
公开(公告)号：US08412867B2
公开(公告)日：2013-04-02
申请号：US12663477
申请日：2008-05-30
申请人： Hiroaki Inoue , Masamichi Takagi , Masaki Uekubo , Sunao Torii , Masato Edahiro
发明人： Hiroaki Inoue , Masamichi Takagi , Masaki Uekubo , Sunao Torii , Masato Edahiro
IPC分类号： G06F13/12 , H04L12/56
CPC分类号： G06F15/16 , G06F21/50 , G06F21/577 , H04L29/06
摘要： A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. The adaptors keep delivery information indicating a delivery condition of a request signal received from the cores and control delivery of the request signal received from the cores in accordance with the delivery information.
摘要翻译：本发明的半导体集成电路包括多个核心，以及包括连接到每个核心的适配器的互连网络以及连接适配器以在它们之间通信的多个路由器。适配器保持指示从核心接收到的请求信号的传送条件的传送信息，并且根据传送信息控制从核心接收的请求信号的传送。

13. 发明授权

US08248073B2 Semiconductor integrated circuit and testing method therefor 有权
标题翻译：半导体集成电路及其测试方法
公开(公告)号：US08248073B2
公开(公告)日：2012-08-21
申请号：US12529458
申请日：2008-02-19
申请人： Hiroaki Inoue , Masamichi Takagi
发明人： Hiroaki Inoue , Masamichi Takagi
IPC分类号： G01V3/00
CPC分类号： G01R31/31724 , G01R31/31723 , G01R31/318536 , G06F11/2236
摘要： A semiconductor integrated circuit comprises a plurality of cores (99) connected with an inter-connection network (1000) and a test controller (500) which is connected with the inter-connection network (1000) and which issues a test control request associated with the test of the core (99) via the inter-connection network (1000). The inter-connection network (1000) is constituted of a plurality of adapters (3000) which serve as connection interfaces of the plurality of cores (99) and the test controller (500), respectively, and a plurality of routers (2000) which connect the plurality of adapters (3000). The adapters (3000) connected with the core (99) comprise a core testing unit for vicariously testing core (99) connected to itself based on the test control request received from the test controller (500) via the inter-connection network (1000).
摘要翻译：半导体集成电路包括与互连网络（1000）连接的多个核（99）和与所述互连网络（1000）连接的测试控制器（500），并且发出与通过互连网络（1000）对核心（99）进行测试。互连网络（1000）由分别用作多个核（99）和测试控制器（500）的连接接口的多个适配器（3000）和多个路由器（2000）组成，多个路由器连接多个适配器（3000）。与核心（99）连接的适配器（3000）包括核心测试单元，用于根据从测试控制器（500）经由互连网络（1000）接收的测试控制请求代替连接到其自身的核心（99）。

14. 发明申请

US20100183015A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND FILTER CONTROL METHOD 有权
标题翻译：半导体集成电路与滤波器控制方法
公开(公告)号：US20100183015A1
公开(公告)日：2010-07-22
申请号：US12663474
申请日：2008-05-30
申请人： Hiroaki Inoue , Masamichi Takagi , Masaki Uekubo , Sunao Torii , Masato Edahiro
发明人： Hiroaki Inoue , Masamichi Takagi , Masaki Uekubo , Sunao Torii , Masato Edahiro
IPC分类号： H04L12/56
CPC分类号： H04L63/0263 , G06F15/7825 , H04L63/0218
摘要： A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. Transmission side adaptors store first delivery information, and control delivery of the request signal to be received from the first core in accordance with the first delivery information. Reception side adaptors store second delivery information, and control delivery of the request signal to be received through the interconnecting network to the second core in accordance with the second delivery information. The first delivery information and the second delivery information are hierarchically set.
摘要翻译：本发明的半导体集成电路包括多个核心，以及包括连接到每个核心的适配器的互连网络以及连接适配器以在它们之间通信的多个路由器。传输侧适配器存储第一传送信息，并且根据第一传送信息控制要从第一内核接收的请求信号的传送。接收侧适配器存储第二传送信息，并且根据第二传送信息控制要通过互连网络接收到第二核的请求信号的传送。第一递送信息和第二递送信息被分层设置。

15. 发明申请

US20100172366A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND FILTER CONTROL METHOD 有权
标题翻译：半导体集成电路和滤波器控制方法
公开(公告)号：US20100172366A1
公开(公告)日：2010-07-08
申请号：US12663477
申请日：2008-05-30
申请人： Hiroaki Inoue , Masamichi Takagi , Masaki Uekubo , Sunao Torii , Masato Edahiro
发明人： Hiroaki Inoue , Masamichi Takagi , Masaki Uekubo , Sunao Torii , Masato Edahiro
IPC分类号： H04L12/56
CPC分类号： G06F15/16 , G06F21/50 , G06F21/577 , H04L29/06
摘要： A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. The adaptors keep delivery information indicating a delivery condition of a request signal received from the cores and control delivery of the request signal received from the cores in accordance with the delivery information.
摘要翻译：本发明的半导体集成电路包括多个核心，以及包括连接到每个核心的适配器的互连网络以及连接适配器以在它们之间通信的多个路由器。适配器保持指示从核心接收到的请求信号的传送条件的传送信息，并且根据传送信息控制从核心接收的请求信号的传送。

16. 发明申请

US20120059020A1 PROPHYLACTIC OR THERAPEUTIC AGENT FOR PULMONARY FIBROSIS 审中-公开
标题翻译：预防或治疗慢性阻塞性肺疾病
公开(公告)号：US20120059020A1
公开(公告)日：2012-03-08
申请号：US13319960
申请日：2009-05-29
申请人： Noboru Hattori , Kentaro Ueda , Makoto Akashima , Masamichi Takagi
发明人： Noboru Hattori , Kentaro Ueda , Makoto Akashima , Masamichi Takagi
IPC分类号： A61K31/505 , A61P11/00 , C07D239/34
CPC分类号： A61K31/505 , C07D239/34
摘要： Disclosed is a compound which has an inhibitory activity on plasminogen activator inhibitor-1 (PAI-1) and has a propanedioic acid structure represented by formula (1) [wherein R1 and R2 independently represent a hydrogen atom or a linear or branched alkyl group having 1 to 4 carbon atoms; R3 represents a cyclohexyl group or a phenyl group (provide that the phenyl group may be substituted by a substituent selected from a linear or branched alkyl group having 1 to 4 carbon atoms, a linear or branched alkoxy group having 1 to 4 carbon atoms, and a halogen atom); R4 represents a linear or branched alkyl group having 1 to 6 carbon atoms or a phenyl group (provide that the phenyl group may be substituted by a substituent selected from a linear or branched alkyl group having 1 to 4 carbon atoms, a linear or branched alkoxy group having 1 to 4 carbon atoms, and a halogen atom); and n represents an integer of 1 to 8]. The compound is useful as a prophylactic or therapeutic agent for pulmonary fibrosis.
摘要翻译：公开了具有对纤溶酶原激活物抑制剂-1（PAI-1）具有抑制活性并具有由式（1）表示的丙二酸结构的化合物[其中R1和R2独立地表示氢原子或具有 1至4个碳原子; R3表示环己基或苯基（提供苯基可以被选自具有1至4个碳原子的直链或支链烷基的取代基，具有1至4个碳原子的直链或支链烷氧基取代，以及卤素原子）; R4表示具有1〜6个碳原子的直链或支链烷基或苯基（提供苯基可以被选自具有1至4个碳原子的直链或支链烷基的取代基取代，直链或支链烷氧基具有1至4个碳原子的基团和卤素原子）; n表示1〜8的整数]。该化合物可用作肺纤维化的预防或治疗剂。

17. 发明授权

US09266543B2 Train protection device and train position decision method 有权
标题翻译：列车保护装置和列车位置决策方法
公开(公告)号：US09266543B2
公开(公告)日：2016-02-23
申请号：US13991245
申请日：2010-12-07
申请人： Masamichi Takagi
发明人： Masamichi Takagi
IPC分类号： B61L25/02 , G01S19/45 , G01S19/50
CPC分类号： B61L25/025 , B61L25/026 , B61L2205/04 , G01S19/45 , G01S19/50
摘要： A train protection device, which decides a position of an own train on track by using GPS satellites, includes: a GPS reception unit; a tachogenerator unit; a track-information storage unit; and a position decision unit. The position decision unit decides the position of the own train based on the GPS signal, the reception state value, the running distance from the reference position, the current speed, and the information of a track on which the own train runs. When the reception state value is equal to or larger than a threshold, the position decision unit decides a position as a current train position by adding, with respect to a forward direction of the track on which the own train runs, a correction value.
摘要翻译：通过使用GPS卫星决定自己的列车在轨道上的位置的列车保护装置包括：GPS接收单元; 一个测速发电机组; 轨道信息存储单元; 和位置决定单元。位置决定单元基于GPS信号，接收状态值，与参考位置的行驶距离，当前速度以及自身列车运行的轨道的信息来决定自身列车的位置。当接收状态值等于或大于阈值时，位置决定单元通过相对于自身列车运行的轨道的前进方向加上校正值来确定作为当前列车位置的位置。

18. 发明授权

US08758741B2 Gene expression cassette and a transformant, and a method for manufacturing 2-deoxy-scyllo-inosose and a method for purifying 2-deoxy-scyllo-inosose using said transformant 有权
标题翻译：基因表达盒和转化体，以及2-脱氧十字鸟苷的制造方法以及使用所述转化体纯化2-脱氧十字鸟苷的方法
公开(公告)号：US08758741B2
公开(公告)日：2014-06-24
申请号：US11887445
申请日：2006-03-23
申请人： Masamichi Takagi , Takahisa Kogure , Naoki Wakisaka , Hiroaki Takaku , Katsumi Ajisaka , Tatsuo Miyazaki , Masao Hirayama
发明人： Masamichi Takagi , Takahisa Kogure , Naoki Wakisaka , Hiroaki Takaku , Katsumi Ajisaka , Tatsuo Miyazaki , Masao Hirayama
IPC分类号： A01N63/00 , C12N15/09 , C12N15/63 , C07H21/04
CPC分类号： C12P17/06 , C07D309/30 , C12N9/88 , C12N9/90 , C12N9/92 , C12P7/26 , C12Y503/01009
摘要： A transformant is prepared to insert at least a gene expression cassette comprising a gene involved in the synthesis of 2-deoxy-scyllo-inosose into E. coli as host cells. A 2-deoxy-scyllo-inosose is synthesized from D-glucose, oligosaccharide, polysaccharide, starch and rice bran, using the transformant. A culture solution containing the 2-deoxy-scyllo-inosose is treated with a mixed bed or double bed type column comprising a hydrogen form of strong acidic cation exchange resin and an organic ion form of basic anion exchange resin. The 2-deoxy-scyllo-inosose as purified is reacted with trimethoxymethane to convert into 2-deoxy-scyllo-inosose dimethylketal, and the dimethylketal is crystallized and purified. Then, DOI is highly purified through hydrolyzing the dimethylketal in the presence of acid.
摘要翻译：制备转化体至少将含有参与合成2-脱氧 - 青蟹肌糖的基因的基因表达盒插入大肠杆菌作为宿主细胞。使用转化体从D-葡萄糖，寡糖，多糖，淀粉和米糠合成2-脱氧 - 青蟹肌糖。含有2-脱氧 - 青蟹肌糖的培养液用含氢形式的强酸性阳离子交换树脂和有机离子形式的碱性阴离子交换树脂的混合床或双床型柱处理。将纯化的2-脱氧 - 青蟹肌糖与三甲氧基甲烷反应以转化成2-脱氧 - 鲨糖醛糖二甲基缩酮，并将二甲基缩酮结晶并纯化。然后，DOI通过在酸存在下水解二甲基缩酮而高度纯化。

19. 发明申请

US20110131578A1 SYSTEMS AND METHODS FOR CHANGING COMPUTATIONAL TASKS ON COMPUTATION NODES TO MINIMIZE PROCESSING TIME VARIATION 有权
标题翻译：用于更改计算节点上计算任务以最小化处理时间变化的系统和方法
公开(公告)号：US20110131578A1
公开(公告)日：2011-06-02
申请号：US12629048
申请日：2009-12-02
申请人： Masamichi Takagi , Yoshiki Seo , Akio Yamada , Takeo Hosomi
发明人： Masamichi Takagi , Yoshiki Seo , Akio Yamada , Takeo Hosomi
IPC分类号： G06F9/46
CPC分类号： G06F9/5038
摘要： Systems and methods are disclosed to process streaming data units (tuples) for an application using a plurality of processing units, the application have a predetermined processing time requirement, by changing an operator-set applied to the tuple by a processing unit, on a tuple-by-tuple basis; estimating code requirement for potential operators based on processing unit capability; and assigning the potential operators to the processing units.
摘要翻译：公开了系统和方法来处理使用多个处理单元的应用的流数据单元（元组），该应用具有预定的处理时间要求，通过在元组上改变由处理单元应用于元组的操作符集元组基于处理单元能力估算潜在运营商的代码要求; 并将潜在的操作者分配给处理单元。

20. 发明申请

US20110067015A1 PROGRAM PARALLELIZATION APPARATUS, PROGRAM PARALLELIZATION METHOD, AND PROGRAM PARALLELIZATION PROGRAM 审中-公开
标题翻译：程序并行化设备，程序并行化方案和程序并行程序
公开(公告)号：US20110067015A1
公开(公告)日：2011-03-17
申请号：US12866219
申请日：2009-02-12
申请人： Masamichi Takagi , Junji Sakai
发明人： Masamichi Takagi , Junji Sakai
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： A program parallelization apparatus which generates a parallelized program of shorter parallel execution time is provided. The program parallelization apparatus inputs a sequential processing intermediate program and outputs a parallelized intermediate program. In the apparatus, a thread start time limitation analysis part analyzes an instruction-allocatable time based on a limitation on an instruction execution start time of each thread. A thread end time limitation analysis part analyzes an instruction-allocatable time based on a limitation on an instruction execution end time of each thread. An occupancy status analysis part analyzes a time not occupied by already-scheduled instructions. A dependence delay analysis part analyzes an instruction-allocatable time based on a delay resulting from dependence between instructions. A schedule candidate instruction select part selects a next instruction to schedule. An instruction arrangement part allocates a processor and time to execute to an instruction.
摘要翻译：提供了一种生成并行执行时间较短并行程序的程序并行化装置。程序并行化装置输入顺序处理中间程序并输出并行化的中间程序。在该装置中，线程开始时间限制分析部分基于对每个线程的指令执行开始时间的限制来分析指令可分配时间。线程结束时间限制分析部分基于对每个线程的指令执行结束时间的限制来分析指令可分配时间。占用状态分析部分分析未被计划的指令占用的时间。依赖延迟分析部分基于由指令之间的依赖导致的延迟来分析指令可分配时间。时间表候选指令选择部分选择要调度的下一个指令。指令排列部分分配处理器和执行指令的时间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式