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11. 发明授权

US4412228A Heat-sensitive recording head driving method 失效
标题翻译：热敏记录头驱动方法
公开(公告)号：US4412228A
公开(公告)日：1983-10-25
申请号：US217606
申请日：1980-12-18
申请人： Haruhiko Moriguchi , Tomio Murayama
发明人： Haruhiko Moriguchi , Tomio Murayama
IPC分类号： B41J2/355 , G01D15/24 , G06K15/10 , H04N1/032 , G01D15/10
CPC分类号： G01D15/24
摘要： A method of driving a heat-sensitive recording head with a very small number of components. In the recording head, leads are arranged on an insulated substrate extending on both sides of the substrate in parallel with one another with heat generating elements disposed between adjacent leads. A microcomputer divides data inputted thereto in a time division manner into data blocks each having a predetermined amount of data. The data in each data block is rearranged by skipping data every predetermined number of data. The data thus rearranged is applied in a parallel mode to a plurality of shift registers and from the shift registers coupled to leads on one side of the recording head successively.
摘要翻译：一种以非常少数量的部件驱动热敏记录头的方法。在记录头中，引线布置在绝缘基板上，彼此平行地延伸在基板的两侧，并且具有设置在相邻引线之间的发热元件。微型计算机将以时分方式输入的数据分割成具有预定数据量的数据块。通过每隔预定数量的数据跳过数据来重新排列每个数据块中的数据。如此重新排列的数据以并行模式施加到多个移位寄存器，并从连接到记录头的一侧上的引线的移位寄存器。

12. 发明授权

US4423520A Quantization circuit for image data transmission system 失效
标题翻译：图像数据传输系统量化电路
公开(公告)号：US4423520A
公开(公告)日：1983-12-27
申请号：US217303
申请日：1980-12-17
申请人： Tomio Murayama , Kenji Koguchi , Shigehumi Takeuchi , Kazumi Tsukioka
发明人： Tomio Murayama , Kenji Koguchi , Shigehumi Takeuchi , Kazumi Tsukioka
IPC分类号： H04N1/407 , H03L7/099 , H04L7/027 , H04N1/00 , H04N7/26 , H03L7/06
CPC分类号： H03L7/0992 , H04L7/027 , H04N1/00095
摘要： A signal receiver quantization circuit for an image data transmission device in which received signals are quantized correctly even if they are subjected to distortion in their time positions so that degradation of the received images is prevented. In accordance with the invention, a signal receiver includes a digital PLL circuit, a PLL control circuit for detecting the transition times of an input received signal with the digital PLL circuit being controlled in accordance with an output of the PLL control circuit, and a circuit for sampling the input signal in response to an output signal of the digital PLL circuit. In a preferred embodiment, the PLL control circuit detects the transition times of the input signal only during predetermined time slots determined in accordance with the relative phase between the input received signal and a sampling clock.
摘要翻译：一种用于图像数据传输装置的信号接收机量化电路，其中接收的信号被正确量化，即使它们在其时间位置遭受失真，从而防止接收到的图像的劣化。根据本发明，信号接收机包括数字PLL电路，用于根据PLL控制电路的输出来控制数字PLL电路的输入接收信号的转换时间的PLL控制电路，以及电路用于响应于数字PLL电路的输出信号对输入信号进行采样。在优选实施例中，PLL控制电路仅在根据输入接收信号和采样时钟之间的相对相位确定的预定时隙期间检测输入信号的转换时间。

13. 发明授权

US4517560A Printing system 失效
标题翻译：印刷系统
公开(公告)号：US4517560A
公开(公告)日：1985-05-14
申请号：US378445
申请日：1982-05-14
申请人： Tomio Murayama , Yoshiki Kikuchi , Takashi Ohmori
发明人： Tomio Murayama , Yoshiki Kikuchi , Takashi Ohmori
IPC分类号： B41J2/00 , G06K15/10 , G06K15/12 , G09G5/28 , G09G3/00 , G01D9/00 , G01D15/18
CPC分类号： G09G5/28 , G06K15/128
摘要： A printing system is provided which allows selected characters or symbols to be emphasized without increasing the density thereof. A video signal containing printing data for a character to be emphasized is delayed and logically added to an undelayed video signal to expand the "black" portion of the signal on the time axis.
摘要翻译：提供一种打印系统，其允许在不增加其浓度的情况下强调所选择的字符或符号。包含要强调的字符的打印数据的视频信号被延迟并逻辑地添加到未延迟的视频信号，以在时间轴上扩展信号的“黑色”部分。

14. 发明授权

US4415933A Carrier wave recovery circuit 失效
标题翻译：载波恢复电路
公开(公告)号：US4415933A
公开(公告)日：1983-11-15
申请号：US216704
申请日：1980-12-15
申请人： Tomio Murayama , Fumio Miyao , Shigefumi Takeuchi , Kazumi Tsukioka
发明人： Tomio Murayama , Fumio Miyao , Shigefumi Takeuchi , Kazumi Tsukioka
IPC分类号： H04L27/06 , H04N1/327 , H03K5/13 , H03L7/00 , H04N1/36
CPC分类号： H04L27/066 , H04N1/327
摘要： A carrier signal recovery circuit to be used in a receiving side of an image information transmitting apparatus, such as in a facsimile system, including an N-bit counter for counting reference clock pulses for a period corresponding to 2.sup.L (L being an integer) cycle periods of the received carrier signal. A first latch holds the most significant bits from the count of the N-bit counter while a second latch holds the least significant bits from the count of the N-bit counter. A frequency divider has a frequency dividing ratio corresponding to one cycle period of the carrier signal with the value of the frequency dividing ratio being initially set by the output of the first latch circuit. An auxiliary counter receiving an input from the second latch provides an output to the frequency divider for correcting the frequency dividing ratio such that the recovered carrier signal is outputted from the frequency divider.
摘要翻译：在图像信息发送装置的接收侧中使用的载波信号恢复电路，例如在传真系统中，包括用于在对应于2L（L为整数）周期的周期中对参考时钟脉冲进行计数的N位计数器接收的载波信号的周期。第一个锁存器保持来自N位计数器的计数的最高有效位，而第二个锁存器保持来自N位计数器的计数的最低有效位。分频器具有对应于载波信号的一个周期周期的分频比，其中分频比的值由第一锁存电路的输出初始设置。从第二锁存器接收输入的辅助计数器向分频器提供输出，用于校正分频比，使得从分频器输出恢复的载波信号。

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