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11. 发明授权

US4155802A Method of producing semiconductor device involving the use of silicon nitride as an oxidation mask 失效
标题翻译：制造涉及使用氮化硅作为氧化掩模的半导体器件的方法
公开(公告)号：US4155802A
公开(公告)日：1979-05-22
申请号：US746898
申请日：1976-12-02
申请人： Toshio Yonezawa , Hidekuni Ishida , Shunichi Hiraki , Shoichi Kitane
发明人： Toshio Yonezawa , Hidekuni Ishida , Shunichi Hiraki , Shoichi Kitane
IPC分类号： H01L29/73 , H01L21/314 , H01L21/316 , H01L21/32 , H01L21/329 , H01L21/331 , H01L21/76 , H01L21/318 , H01L21/308
CPC分类号： H01L21/3144 , H01L21/32
摘要： A method of producing a semiconductor device comprises removing all of the masking films used for forming desired semiconductor regions in the substrate, newly forming an insulation film and selectively forming a second insulation film at predetermined portions by the use of a silicon nitride film as the mask.
摘要翻译：一种制造半导体器件的方法包括：通过使用氮化硅膜作为掩模，除去用于在衬底中形成期望的半导体区域的所有掩模膜，新形成绝缘膜并且在预定部分选择性地形成第二绝缘膜。

12. 发明授权

US5554872A Semiconductor device and method of increasing device breakdown voltage of semiconductor device 失效
标题翻译：半导体器件的器件击穿电压提高的半导体器件及方法
公开(公告)号：US5554872A
公开(公告)日：1996-09-10
申请号：US412215
申请日：1995-03-27
申请人： Yoshiro Baba , Shunichi Hiraki , Akihiko Osawa
发明人： Yoshiro Baba , Shunichi Hiraki , Akihiko Osawa
IPC分类号： H01L21/762 , H01L27/02 , H01L27/08 , H01L29/10 , H01L29/78 , H01L29/861 , H01L29/76
CPC分类号： H01L29/7824 , H01L27/0218 , H01L29/1087 , Y10S257/901
摘要： In a semiconductor device including a composite substrate formed by bonding first and second semiconductor substrates to each other through an oxide film and an insulator isolation trench formed from a major surface of the first semiconductor substrate to reach the oxide film and to surround an element forming region, when the potential of the second substrate is set at a potential higher than the minimum potential in the element forming region of the first substrate, an breakdown voltage can be increased. In a semiconductor integrated circuit having an element isolation region, a semiconductor device of a perfect dielectric isolation structure having an element forming region having a thickness smaller than that of the element forming region of a P-N junction isolation structure is used to reduce, e.g., a base curvature influence, thereby obtaining a further high breakdown voltage.
摘要翻译：在包括通过氧化膜将第一和第二半导体衬底彼此接合而形成的复合衬底的半导体器件和由第一半导体衬底的主表面形成的绝缘体隔离沟槽到达氧化膜并且围绕元件形成区域当第二基板的电位设定为高于第一基板的元件形成区域中的最小电位的电位时，可以提高击穿电压。在具有元件隔离区域的半导体集成电路中，使用具有比PN结隔离结构的元件形成区域的厚度小的元件形成区域的完美电介质隔离结构的半导体器件，以减少例如基础曲率影响，从而获得更高的击穿电压。

13. 发明授权

US4451303A Diffusion of aluminum 失效
标题翻译：铝的扩散
公开(公告)号：US4451303A
公开(公告)日：1984-05-29
申请号：US455795
申请日：1983-01-05
申请人： Shunichi Hiraki , Kiyoshi Kikuchi , Shigeo Yawata , Masafumi Miyagawa
发明人： Shunichi Hiraki , Kiyoshi Kikuchi , Shigeo Yawata , Masafumi Miyagawa
IPC分类号： H01L21/225 , H01L21/265
CPC分类号： H01L21/2256
摘要： A method for producing a semiconductor element which can form a deep P-type impurity region by a diffusion of aluminum. A porous alumina layer is first formed on a semiconductor substrate. Then, a diffusion-protective layer formed of a material having a large oxygen-diffusion-inhibiting ability such as Al.sub.2 O.sub.3 is formed on the porous alumina layer. Subsequently, aluminum ions are implanted in the porous alumina layer through the diffusion-protective layer. Thereafter, a heat treatment is performed to diffuse the aluminum of the aluminum ion-implanted region in the semiconductor substrate, and a P-type impurity region is formed. Alternatively, a porous alumina layer is formed on the semiconductor substrate, and an aluminum layer is then formed thereon. The diffusion-protective layer is formed on the aluminum layer, and a heat treatment is then performed, thereby diffusing the aluminum forming the aluminum layer in the semiconductor substrate, and a P-type impurity region is thus formed.
摘要翻译：一种可通过铝的扩散形成深P型杂质区的半导体元件的制造方法。首先在半导体衬底上形成多孔氧化铝层。然后，在多孔氧化铝层上形成由具有大的氧扩散抑制能力的材料形成的扩散保护层，如Al2O3。随后，通过扩散保护层将铝离子注入到多孔氧化铝层中。此后，进行热处理以使半导体衬底中的铝离子注入区的铝扩散，形成P型杂质区。或者，在半导体衬底上形成多孔氧化铝层，然后在其上形成铝层。在铝层上形成扩散保护层，然后进行热处理，从而使形成铝层的铝在半导体衬底中扩散，由此形成P型杂质区。

14. 发明授权

US4647472A Process of producing a semiconductor device 失效
标题翻译：制造半导体器件的工艺
公开(公告)号：US4647472A
公开(公告)日：1987-03-03
申请号：US758854
申请日：1985-07-26
申请人： Shunichi Hiraki , Yoshikazu Usuki , Kazuhiro Takimoto
发明人： Shunichi Hiraki , Yoshikazu Usuki , Kazuhiro Takimoto
IPC分类号： H01L21/314 , H01L23/29 , H01L23/31 , H01L23/60 , B05D3/06
CPC分类号： H01L23/60 , H01L21/314 , H01L23/291 , H01L23/3178 , H01L2924/0002 , H01L2924/3025 , Y10S438/902 , Y10S438/958
摘要： A semiconductor device which has a protective film having a high blocking capacity against contaminating ions and a high shielding effect against an external electric field. The protective film is formed on a surface of the semiconductor device. The protective film consists essentially of an amorphous or polycrystalline silicon carbide which contains at least one element selected from the group consisting of hydrogen, nitrogen, oxygen and a halogen.
摘要翻译：一种半导体器件，其具有对污染离子具有高阻隔能力的保护膜和对外部电场的高屏蔽效应。保护膜形成在半导体器件的表面上。保护膜基本上由非晶或多晶碳化硅组成，其含有至少一种选自氢，氮，氧和卤素的元素。

15. 发明授权

US5242845A Method of production of vertical MOS transistor 失效
标题翻译：垂直MOS晶体管的制造方法
公开(公告)号：US5242845A
公开(公告)日：1993-09-07
申请号：US866418
申请日：1992-04-10
申请人： Yoshiro Baba , Shunichi Hiraki , Akihiko Osawa , Satoshi Yanagiya
发明人： Yoshiro Baba , Shunichi Hiraki , Akihiko Osawa , Satoshi Yanagiya
IPC分类号： H01L29/06 , H01L29/40 , H01L29/423 , H01L29/78
CPC分类号： H01L29/402 , H01L29/407 , H01L29/42368 , H01L29/7813 , H01L29/4232 , H01L29/4238 , H01L29/7831
摘要： A vertical MOS transistor comprises a semiconductor substrate, a first impurity region defined on the surface of the semiconductor substrate, a second impurity region defined under the first impurity region, the conduction type of the second impurity region being opposite to that of the first impurity region, a trench engraved on the surface of the semiconductor substrate to cut through the first and second impurity regions deeper than at least the bottom of the second impurity region, and a gate electrode disposed in the trench with a gate insulation film interposing between the wall of the trench and the gate electrode. The gate insulation film is thicker on the bottom of the trench and on part of the side walls of the trench continuous to the bottom than on the other parts.
摘要翻译：垂直MOS晶体管包括半导体衬底，限定在半导体衬底的表面上的第一杂质区域，限定在第一杂质区域下方的第二杂质区域，第二杂质区域的导电类型与第一杂质区域的导电类型相反刻蚀在所述半导体衬底的表面上的沟槽，以切割穿过所述第一和第二杂质区域至少比所述第二杂质区域的底部更深;以及栅电极，设置在所述沟槽中，栅极绝缘膜插入在所述第二杂质区域的壁之间沟槽和栅电极。栅极绝缘膜在沟槽的底部和沟槽的侧壁的一部分比底部更厚，而不是其它部分。

16. 发明授权

US5126807A Vertical MOS transistor and its production method 失效
标题翻译：垂直MOS晶体管及其制作方法
公开(公告)号：US5126807A
公开(公告)日：1992-06-30
申请号：US713505
申请日：1991-06-12
申请人： Yoshiro Baba , Shunichi Hiraki , Akihiko Osawa , Satoshi Yanagiya
发明人： Yoshiro Baba , Shunichi Hiraki , Akihiko Osawa , Satoshi Yanagiya
IPC分类号： H01L29/06 , H01L29/40 , H01L29/423 , H01L29/78
CPC分类号： H01L29/402 , H01L29/407 , H01L29/42368 , H01L29/42376 , H01L29/7813
摘要： A vertical MOS transistor comprises a semiconductor substrate, a first impurity region defined on the surface of the semiconductor substrate, a second impurity region defined under the first impurity region, the conduction type of the second impurity region being opposite to that of the first impurity region, a trench engraved on the surface of the semiconductor substrate to cut through the first and second impurity regions deeper than at least the bottom of the second impurity region, and a gate electrode disposed in the trench with a gate insulation film interposing between the wall of the trench and the gate electrode. THE gate insulation film is thicker on the bottom of the trench and on part of the side walls of the trench continuous to the bottom than on the other parts.
摘要翻译：垂直MOS晶体管包括半导体衬底，限定在半导体衬底的表面上的第一杂质区域，限定在第一杂质区域下方的第二杂质区域，第二杂质区域的导电类型与第一杂质区域的导电类型相反刻蚀在所述半导体衬底的表面上的沟槽，以切割穿过所述第一和第二杂质区域至少比所述第二杂质区域的底部更深;以及栅电极，设置在所述沟槽中，栅极绝缘膜插入在所述第二杂质区域的壁之间沟槽和栅电极。栅极绝缘膜在沟槽的底部和沟槽的侧壁的一部分比底部的部分更厚，而不是其他部分。

17. 发明授权

US5321289A Vertical MOSFET having trench covered with multilayer gate film 失效
标题翻译：具有覆盖有多层栅极膜的沟槽的垂直MOSFET
公开(公告)号：US5321289A
公开(公告)日：1994-06-14
申请号：US139142
申请日：1993-10-21
申请人： Yoshiro Baba , Satoshi Yanagiya , Noburo Matsuda , Shunichi Hiraki
发明人： Yoshiro Baba , Satoshi Yanagiya , Noburo Matsuda , Shunichi Hiraki
IPC分类号： H01L29/423 , H01L29/51 , H01L29/78 , H01L29/10
CPC分类号： H01L29/7813 , H01L29/513 , H01L29/518 , H01L29/4236 , H01L29/511
摘要： A vertical MOSFET includes a trench whose inner surface is covered with an insulating layer having a multilayer structure. In order to reduce a change in a gate threshold voltage, and equivalent silicon dioxide thickness of the gate insulating layer and a radius of curvature of an upper corner of the trench are provided such that a dielectric breakdown electric field strength of the gate insulating layer at the upper corner is in the range of 2.5 MV/cm to 5.0 MV/cm.
摘要翻译：垂直MOSFET包括其内表面被具有多层结构的绝缘层覆盖的沟槽。为了减小栅极阈值电压的变化，并且提供栅极绝缘层的等效二氧化硅厚度和沟槽的上角的曲率半径，使得栅极绝缘层的介电击穿电场强度在上角处于2.5MV / cm至5.0MV / cm的范围内。

18. 发明授权

US5282018A Power semiconductor device having gate structure in trench 失效
标题翻译：在沟槽中具有栅极结构的功率半导体器件
公开(公告)号：US5282018A
公开(公告)日：1994-01-25
申请号：US53811
申请日：1993-04-29
申请人： Shunichi Hiraki , Yoshiro Baba
发明人： Shunichi Hiraki , Yoshiro Baba
IPC分类号： H01L21/74 , H01L27/088 , H01L29/423 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/74 , H01L27/088 , H01L29/7397 , H01L29/4236
摘要： A power MOS semiconductor device, such as a vertical MOSFET, IGBT, and IPD, includes a body of semiconductor material having a first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type and formed in the first semiconductor layer to provide a channel, a third semiconductor layer having the first conductivity type and formed in the second semiconductor layer, a trench formed in the first semiconductor layer across the third and second semiconductor layers, a gate insulating film covering a surface of the trench and extending to a surface of the third semiconductor layer, a gate electrode layer provided on the gate insulating film, and a buried layer having the first conductivity type provided in the first semiconductor layer so as to be contiguous to a bottom of the trench.
摘要翻译：诸如垂直MOSFET，IGBT和IPD的功率MOS半导体器件包括具有第一导电类型的第一半导体层的半导体材料体，具有第二导电类型的第二半导体层，并形成在第一半导体层为了提供通道，具有第一导电类型并形成在第二半导体层中的第三半导体层，形成在跨越第三和第二半导体层的第一半导体层中的沟槽，覆盖沟槽表面并延伸的栅绝缘膜在所述第三半导体层的表面上设置设置在所述栅极绝缘膜上的栅电极层，以及设置在所述第一半导体层中以与所述沟槽的底部邻接的具有所述第一导电类型的掩埋层。

19. 发明授权

US4729966A Process for manufacturing a Schottky FET device using metal sidewalls as gates 失效
标题翻译：使用金属侧壁作为栅极制造肖特基FET器件的工艺
公开(公告)号：US4729966A
公开(公告)日：1988-03-08
申请号：US843833
申请日：1986-03-26
申请人： Yutaka Koshino , Tatsuo Akiyama , Shunichi Hiraki
发明人： Yutaka Koshino , Tatsuo Akiyama , Shunichi Hiraki
IPC分类号： H01L29/812 , H01L21/28 , H01L21/285 , H01L21/338 , H01L29/417 , H01L21/225 , H01L29/72 , H01L29/80
CPC分类号： H01L29/66878 , H01L21/2815 , H01L21/28587
摘要： A first insulative film is formed with predetermined height and thickness in a loop shape on the surface of the Schottky-junction semiconductor substrate. A gate electrode metal film is formed with a predetermined height and thickness in a loop shape on the surface of the substrate along the inner surface of the first insulative film. A second insulative film is formed with a predetermined height and thickness in a loop shape on the surface of the substrate along the inner surface of the metal film. A channel consisting of a low concentration impurity layer, is formed in a loop shape inside the substrate directly under the metal film and the first and second insulative films. The source region consists of a high-concentration impurity layer formed such that it surrounds the channel positioned inside the substrate on the outside of the first insulative film. The drain region consists of a high-concentration impurity layer, which is formed such that it is surrounded by the channel positioned inside the substrate on the inside of the second insulative film.
摘要翻译：第一绝缘膜在肖特基结半导体衬底的表面上以环形形成预定的高度和厚度。栅极电极金属膜沿着第一绝缘膜的内表面在基板的表面上以环形形成预定的高度和厚度。第二绝缘膜沿着金属膜的内表面在基板的表面上以环形形成预定的高度和厚度。由低浓度杂质层构成的通道在金属膜正下方的基板内部以及第一绝缘膜和第二绝缘膜之间形成为环状。源极区域由高浓度杂质层构成，其形成为使得其围绕位于第一绝缘膜外侧的衬底内的沟道。漏极区域由高浓度杂质层构成，其形成为被位于第二绝缘膜内侧的位于基板内部的沟道包围。

20. 发明授权

US4532004A Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US4532004A
公开(公告)日：1985-07-30
申请号：US636221
申请日：1984-07-31
申请人： Tatsuo Akiyama , Yutaka Koshino , Shunichi Hiraki
发明人： Tatsuo Akiyama , Yutaka Koshino , Shunichi Hiraki
IPC分类号： H01L21/033 , H01L21/285 , H01L21/338 , H01L29/417 , H01L29/80 , H01L29/812 , H01L21/306 , B44C1/22 , C03C15/00 , C23F1/02
CPC分类号： H01L29/66871 , H01L21/033 , H01L21/28587 , H01L29/80 , H01L29/812
摘要： A method of manufacturing a GaAs FET is disclosed. In this manufacturing method, a protection film is formed on a GaAs substrate and a dummy gate electrode is formed thereon. A channel length setting film is isotropically formed on the dummy gate electrode to have a constant thickness. Then, an impurity is ion-implanted in the channel length setting film. Thereafter, the channel length setting film is removed. An etching preventive film is anisotropically formed along a substantially vertical direction with respect to the GaAs substrate. The dummy gate electrode is etched using the etching preventive film as a mask so as to form a first opening in the etching preventive film. Then, a second opening is formed in the region of the protection film corresponding to the region in which the dummy gate electrode was present. A gate electrode is formed to be in contact with the GaAs substrate through the first and second openings.
摘要翻译：公开了一种制造GaAs FET的方法。在该制造方法中，在GaAs衬底上形成保护膜，在其上形成虚拟栅电极。通道长度设定膜在虚拟栅电极上各向同性地形成，以具有恒定的厚度。然后，在沟道长度设定膜中离子注入杂质。此后，去除通道长度设定膜。蚀刻防止膜相对于GaAs衬底沿大致垂直方向各向异性地形成。使用防蚀膜作为掩模蚀刻伪栅电极，以在防蚀膜中形成第一开口。然后，在保护膜的与存在虚拟栅电极的区域相对应的区域中形成第二开口。栅电极通过第一和第二开口形成为与GaAs衬底接触。

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