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11. 发明申请

US20060263231A1 Method for making a compositionally graded gas turbine disk 失效
公开(公告)号：US20060263231A1
公开(公告)日：2006-11-23
申请号：US11229823
申请日：2005-09-19
申请人： Jon Groh , Eric Ott , Robert Schafrik , Daniel Krueger
发明人： Jon Groh , Eric Ott , Robert Schafrik , Daniel Krueger
IPC分类号： B22F7/00
CPC分类号： F01D5/02 , B22F3/004 , B22F3/1208 , B22F5/009 , B22F7/06 , B22F2998/00 , B22F2998/10 , B22F2999/00 , B23P15/006 , F01D25/005 , F05C2253/24 , F05D2230/22 , F05D2230/311 , F05D2230/312 , Y02T50/671 , Y10T29/4932 , Y10T29/49325 , B22F3/15 , B22F3/20 , B22F3/17 , B22F5/08 , B22F2207/01 , B22F1/0003 , B22F3/02 , B22F1/0085 , B22F3/1017 , B22F2207/15
摘要： A compositionally graded gas turbine disk is made by placing a cylindrically symmetric slip case concentrically into an interior of a cylindrically symmetric outer container. A first nickel-base superalloy powder is loaded into a radially inner first portion of the interior and a second nickel-base superalloy powder is loaded into a radially outer second portion of the interior. The slip case is removed so that the first nickel-base superalloy powder and the second nickel-base superalloy powder contact in the transition region and form a non-compacted powder mass. The non-compacted powder mass is processed into a gas turbine disk, typically by compacting the non-compacted powder mass to form a compacted powder mass, and thereafter heat treating the compacted powder mass.

12. 发明申请

US20060260126A1 Method for making a compositionally graded gas turbine disk 失效
标题翻译：制造成分分级的燃气轮机盘的方法
公开(公告)号：US20060260126A1
公开(公告)日：2006-11-23
申请号：US11130764
申请日：2005-05-17
申请人： Jon Groh , Eric Ott , Robert Schafrik , Daniel Krueger
发明人： Jon Groh , Eric Ott , Robert Schafrik , Daniel Krueger
IPC分类号： B23P15/04
CPC分类号： F01D5/02 , B22F3/004 , B22F3/1208 , B22F5/009 , B22F7/06 , B22F2998/00 , B22F2998/10 , B22F2999/00 , B23P15/006 , F01D25/005 , F05C2253/24 , F05D2230/22 , F05D2230/311 , F05D2230/312 , Y02T50/671 , Y10T29/4932 , Y10T29/49325 , B22F3/15 , B22F3/20 , B22F3/17 , B22F5/08 , B22F2207/01 , B22F1/0003 , B22F3/02 , B22F1/0085 , B22F3/1017 , B22F2207/15
摘要： A compositionally graded gas turbine disk is made by preparing a rotationally symmetric radially inner segment of a gas turbine disk preform, rotating the inner segment about a central axis, spray applying a radially outer-segment material onto the radially inner segment as it rotates about the central axis, preferably achieving a gradual transition in composition, and thereafter further processing the gas turbine disk preform to produce the compositionally graded gas turbine disk.
摘要翻译：通过制备燃气涡轮盘预制件的旋转对称的径向内部段，通过使内部区段围绕中心轴线旋转来制造成分分级的燃气轮机盘，当径向内部段旋转时，将径向外部段材料喷射到径向内部段上中心轴，优选地实现组成的逐渐过渡，然后进一步处理燃气涡轮盘预制件以产生组成分级的燃气轮机盘。

13. 发明申请

US20060103442A1 Memory element with improved soft-error rate 审中-公开
标题翻译：具有改善的软错误率的存储器元件
公开(公告)号：US20060103442A1
公开(公告)日：2006-05-18
申请号：US10993014
申请日：2004-11-18
申请人： Daniel Krueger
发明人： Daniel Krueger
IPC分类号： H03K3/356
CPC分类号： G11C11/4125
摘要： In a preferred embodiment, the invention provides a circuit and method for reducing soft error events in memory elements. A first transfer gate is connected to an first input of a first tristatable inverter, a second input of a second tristatable inverter, and the output of a third tristatable inverter. A second transfer gate is connected to an first input of the second tristatable inverter, a second input of the first tristatable inverter, and the output of a fourth tristatable inverter. The output of the first tristatable inverter is connected to the first input of the third tristatable inverter and the second input of the fourth tristatable inverter. The output of the second tristatable inverter is connected to the second input of the third tristatable inverter and the first input of the fourth tristatable inverter. The input of an inverter is connected to the output of the fourth tristatable inverter.
摘要翻译：在优选实施例中，本发明提供一种用于减少存储器元件中的软错误事件的电路和方法。第一传输门连接到第一可跟踪逆变器的第一输入端，第二可跟踪逆变器的第二输入端和第三可跟踪反相器的输出端。第二传输门连接到第二可跟踪逆变器的第一输入端，第一可跟踪逆变器的第二输入端和第四可跟踪逆变器的输出端。第一可跟踪逆变器的输出连接到第三可跟踪逆变器的第一输入端和第四可跟踪逆变器的第二输入端。第二可跟踪逆变器的输出连接到第三可跟踪逆变器的第二输入端和第四可跟踪逆变器的第一输入端。逆变器的输入端连接到第四可调整逆变器的输出端。

14. 发明申请

US20050144580A1 Method and system for testing a logic design 审中-公开
标题翻译：用于测试逻辑设计的方法和系统
公开(公告)号：US20050144580A1
公开(公告)日：2005-06-30
申请号：US10732394
申请日：2003-12-10
申请人： Daniel Berkram , Daniel Krueger
发明人： Daniel Berkram , Daniel Krueger
IPC分类号： G01R31/317 , G06F9/45 , G06F17/50
CPC分类号： G06F17/5022 , G01R31/31704
摘要： A method of testing a logic design in one disclosed embodiment includes identifying a plurality of clocked logic elements of a first logic design. The plurality of logic elements is subdivided into M individual groups of elements. A distinct pseudo-clock is assigned to each of the M groups such that each of the M groups of logic elements is associated with a distinct clock domain in a second logic design. A simulation is performed on the second logic design with the M pseudo-clocks.
摘要翻译：在一个公开的实施例中测试逻辑设计的方法包括识别第一逻辑设计的多个时钟逻辑元件。多个逻辑元件被细分成M个单独的元件组。将不同的伪时钟分配给每个M组，使得M组的逻辑元件中的每一个在第二逻辑设计中与不同的时钟域相关联。在M个伪时钟的第二个逻辑设计上进行仿真。

15. 发明授权

US06594772B1 Clock distribution circuitry to different nodes on integrated circuit with clock coupling circuitry to maintain predetermined phase relation between output and input of adjacent nodes 失效
标题翻译：时钟分配电路到具有时钟耦合电路的集成电路上的不同节点，以保持相邻节点的输出和输入之间的预定相位关系
公开(公告)号：US06594772B1
公开(公告)日：2003-07-15
申请号：US09483283
申请日：2000-01-14
申请人： Li C Tsai , Daniel Krueger , Johnny Q Zhang
发明人： Li C Tsai , Daniel Krueger , Johnny Q Zhang
IPC分类号： G06F104
CPC分类号： G06F1/10 , H03K5/15013 , H03L7/0812
摘要： Integrated circuit clock circuitry includes several clock nodes at different locations on a chip. Each node includes a clock wave input, a clock wave output and feedback circuitry for maintaining a predetermined phase relation between clock waves at the clock wave inputs and outputs. The clock wave input of one of the nodes is directly responsive to a clock wave of a clock wave source. A clock coupling circuit connected between each of the clock wave inputs (except the clock wave input of the node directly responsive to the clock wave source) and each of the clock wave outputs couples clock waves from the clock wave output of a first node to a clock wave input of a second node. Each of the coupling circuits includes feedback circuitry for maintaining a predetermined phase relation between clock waves the first node supplies to the coupling circuit and derived by the coupling circuit. A measure of clock wave skew of the integrated circuit chip is obtained by connecting a clock coupling circuit and a separate node in a path extending between the most distant nodes on the chip. The path includes a phase detector responsive to clock waves supplied to the distantly spaced node and the node of the path extending between the most distant nodes on the chip.
摘要翻译：集成电路时钟电路在芯片上的不同位置包括几个时钟节点。每个节点包括时钟波输入，时钟波输出和反馈电路，用于在时钟波输入和输出端保持时钟波之间的预定相位关系。其中一个节点的时钟波输入直接响应于时钟波源的时钟波。连接在每个时钟波输入（除了直接响应于时钟波源的节点的时钟波输入之外）和每个时钟波输出之间的时钟耦合电路将时钟波从第一节点的时钟波输出耦合到第二个节点的时钟波输入。每个耦合电路包括反馈电路，用于维持第一节点向耦合电路提供并由耦合电路导出的时钟波之间的预定相位关系。通过在芯片上最远的节点之间延伸的路径中连接时钟耦合电路和单独的节点来获得集成电路芯片的时钟波形偏移的度量。该路径包括响应于提供给间隔远的节点的时钟波和在芯片上最远处节点之间延伸的路径的节点的相位检测器。

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