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11. 发明授权

US08145732B2 Live network configuration within a link based computing system 有权
标题翻译：基于链路的计算系统中的实时网络配置
公开(公告)号：US08145732B2
公开(公告)日：2012-03-27
申请号：US11284537
申请日：2005-11-21
申请人： Mohan J. Kumar , Murugasamy Nachimuthu , Allen Baum
发明人： Mohan J. Kumar , Murugasamy Nachimuthu , Allen Baum
IPC分类号： G06F15/177 , G06F15/173 , G06F15/16 , G06F11/00 , G06F9/44 , G06F9/445 , H04L12/28 , H04B1/38 , G06Q10/00 , G06Q30/00
CPC分类号： H04L41/082
摘要： A method is described in which, in response to notice of a configuration event yet to happen within a network that is part of a link-based computing system, a component within said link based computing system: a) identifies networking configuration information changes to be made by components within the link-based computing system; and, b) sends instances of program code to each one of the components. Each instance of program code is to be executed by a specific component that it was sent to. Each instance of program code is customized to implement the particular one or more networking configuration information changes to be made at the specific component it was sent to.
摘要翻译：描述了一种方法，其中响应于在作为基于链路的计算系统的一部分的网络内尚未发生的配置事件的通知，所述基于链路的计算系统中的组件：a）将网络配置信息变化标识为由基于链路的计算系统中的组件构成; 和b）将程序代码的实例发送到每个组件。程序代码的每个实例都要由发送到的特定组件来执行。程序代码的每个实例被定制以实现要在其发送到的特定组件上进行的特定一个或多个网络配置信息更改。

12. 发明授权

US07856551B2 Dynamically discovering a system topology 有权
标题翻译：动态发现系统拓扑
公开(公告)号：US07856551B2
公开(公告)日：2010-12-21
申请号：US11810434
申请日：2007-06-05
申请人： Xiaohua Cai , Yufu Li , Murugasamy Nachimuthu , Rahul Khanna , Koo Heng Daniel AW , Wenson Lin
发明人： Xiaohua Cai , Yufu Li , Murugasamy Nachimuthu , Rahul Khanna , Koo Heng Daniel AW , Wenson Lin
IPC分类号： G06F9/00
CPC分类号： G06F15/17337 , G06F15/177
摘要： In one embodiment, the present invention includes a method for dynamically discovering a topology of a system having a plurality of point-to-point (PTP) links via a routine that communicates a link exchanged parameter with at least one component coupled to a system bootstrap processor (SBSP), sets a minimal set of routing infrastructure information based on the communication, and determines presence of a neighboring component to a target component based on a communication from the SBSP to the target component using the minimal set of routing infrastructure information. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于动态发现具有多个点对点（PTP）链路的系统的拓扑的方法，所述系统经由将链路交换的参数与耦合到系统引导的至少一个组件进行通信的例程处理器（SBSP）基于通信设置最小的路由基础设施信息集合，并且基于使用最小路由基础设施信息集从SBSP到目标组件的通信来确定邻近组件到目标组件的存在。描述和要求保护其他实施例。

13. 发明申请

US20090083528A1 SYSTEM INFORMATION SYNCHRONIZATION IN A LINKS-BASED MULTI-PROCESSOR SYSTEM 有权
标题翻译：基于链路的多处理器系统中的系统信息同步
公开(公告)号：US20090083528A1
公开(公告)日：2009-03-26
申请号：US11859640
申请日：2007-09-21
申请人： Yufu Li , XiaoHua Cai , Rahul Khanna , Murugasamy Nachimuthu , Vincent J. Zimmer
发明人： Yufu Li , XiaoHua Cai , Rahul Khanna , Murugasamy Nachimuthu , Vincent J. Zimmer
IPC分类号： G06F15/76 , G06F15/167 , G06F9/02 , G06F15/177
CPC分类号： G06F15/177 , G06F9/4405
摘要： Various embodiments described herein include one or more of systems, methods, firmware, and software to synchronize system information between processors during system boot in a links-based multi-processor system. Some embodiments synchronize data block by block through memory rather than piece by piece through registers by allowing a System Bootstrap Processor (“SBSP”) to directly access synchronization data in local memory of each of one or more Application Processors. These and other embodiments are described in greater detail below.
摘要翻译：本文描述的各种实施例包括在基于链路的多处理器系统中的系统引导期间在处理器之间同步系统信息的系统，方法，固件和软件中的一个或多个。一些实施例通过允许系统引导处理器（“SBSP”）直接访问一个或多个应用处理器中的每一个的本地存储器中的同步数据，通过存储器而不是通过寄存器逐块同步数据。下面更详细地描述这些和其它实施例。

14. 发明申请

US20080162982A1 METHODS AND APPARATUS TO CHANGE A CONFIGURATION OF A PROCESSOR SYSTEM 失效
标题翻译：改变处理器系统配置的方法和设备
公开(公告)号：US20080162982A1
公开(公告)日：2008-07-03
申请号：US11618422
申请日：2006-12-29
申请人： Yufu Li , Jian Tang , XiaoHua Cai , Murugasamy Nachimuthu , Rahul Khanna
发明人： Yufu Li , Jian Tang , XiaoHua Cai , Murugasamy Nachimuthu , Rahul Khanna
IPC分类号： G06F11/00
CPC分类号： G06F9/4812 , G06F9/5061
摘要： Methods and apparatus to change a configuration of a processor system are disclosed. An example disclosed method calculates system configuration data during a non-quiesce state of a processing system, stores information based on the calculated system configuration data in a data buffer during the non-quiesce state of the processing system, and extracts information from the data buffer to update the configuration of the processing system while the processing system is in a quiesce state.
摘要翻译：公开了改变处理器系统的配置的方法和装置。一个示例公开的方法在处理系统的非静默状态期间计算系统配置数据，在处理系统的非静止状态期间将基于所计算的系统配置数据的信息存储在数据缓冲器中，并且从数据缓冲器中提取信息在处理系统处于静止状态时更新处理系统的配置。

15. 发明申请

US20070220332A1 Configurable error handling apparatus and methods to operate the same 有权
标题翻译：可配置的错误处理设备和操作方法
公开(公告)号：US20070220332A1
公开(公告)日：2007-09-20
申请号：US11352961
申请日：2006-02-13
申请人： Suresh Marisetty , Baskaran Ganesan , Gautam Doshi , Murugasamy Nachimuthu , Koichi Yamada , Jose Vargas , Jim Crossland , Stan Domen
发明人： Suresh Marisetty , Baskaran Ganesan , Gautam Doshi , Murugasamy Nachimuthu , Koichi Yamada , Jose Vargas , Jim Crossland , Stan Domen
IPC分类号： G06F11/00
CPC分类号： G06F11/0772 , G06F11/0781
摘要： Configurable error handling apparatus and methods to operate the same are disclosed. An example apparatus comprises a processor core in a semiconductor package, a hardware functional block in the semiconductor package, an error handler in the semiconductor package, wherein the error handler is configurable to route error data from the hardware functional block to at least one of a first error log or a second error log and to route error signals from the hardware functional block to at least one of an operating system or firmware, and wherein the processor core configures the error handler and the hardware functional block.
摘要翻译：公开了可配置的误差处理装置及其操作方法。示例性设备包括半导体封装中的处理器核心，半导体封装中的硬件功能块，半导体封装中的错误处理器，其中错误处理程序可配置为将错误数据从硬件功能块路由到至少一个第一错误日志或第二错误日志，并将来自硬件功能块的错误信号路由到操作系统或固件中的至少一个，并且其中处理器核心配置错误处理程序和硬件功能块。

16. 发明申请

US20070118628A1 Live network configuration within a link based computing system 有权
标题翻译：基于链路的计算系统中的实时网络配置
公开(公告)号：US20070118628A1
公开(公告)日：2007-05-24
申请号：US11284537
申请日：2005-11-21
申请人： Mohan Kumar , Murugasamy Nachimuthu , Allen Baum
发明人： Mohan Kumar , Murugasamy Nachimuthu , Allen Baum
IPC分类号： G06F15/177
CPC分类号： H04L41/082
摘要： A method is described in which, in response to notice of a configuration event yet to happen within a network that is part of a link-based computing system, a component within said link based computing system: a) identifies networking configuration information changes to be made by components within the link-based computing system; and, b) sends instances of program code to each one of the components. Each instance of program code is to be executed by a specific component that it was sent to. Each instance of program code is customized to implement the particular one or more networking configuration information changes to be made at the specific component it was sent to.
摘要翻译：描述了一种方法，其中响应于在作为基于链路的计算系统的一部分的网络内尚未发生的配置事件的通知，所述基于链路的计算系统中的组件：a）将网络配置信息变化标识为由基于链路的计算系统中的组件构成; 和b）将程序代码的实例发送到每个组件。程序代码的每个实例都要由发送到的特定组件来执行。程序代码的每个实例被定制以实现要在其发送到的特定组件上进行的特定一个或多个网络配置信息更改。

17. 发明申请

US20160232103A1 BLOCK STORAGE APERTURES TO PERSISTENT MEMORY 审中-公开
标题翻译：对存储记忆体的存储存储空间
公开(公告)号：US20160232103A1
公开(公告)日：2016-08-11
申请号：US14127553
申请日：2013-09-26
申请人： Mark A. Schmisseur , Andy M. Rudoff , Murugasamy Nachimuthu , Mahesh S. Natu , Richard P. Mangold , Douglas D. Stewart
发明人： Mark A. Schmisseur , Andy M. Rudoff , Murugasamy Nachimuthu , Mahesh S. Natu , Richard P. Mangold , Douglas D. Stewart
IPC分类号： G06F12/10 , G06F11/07 , G06F13/16 , G06F12/14 , G06F3/06
CPC分类号： G06F12/10 , G06F3/061 , G06F3/0622 , G06F3/0659 , G06F3/0679 , G06F11/073 , G06F11/0772 , G06F12/0246 , G06F12/1408 , G06F12/1441 , G06F13/1668 , G06F2212/1052 , G06F2212/202 , G06F2212/2022 , G06F2212/402 , G06F2212/7201
摘要： Apparatus and methods for accessing a non-volatile memory (NVM) device in a computer system that includes at least one host processor and at least one memory bus. The NVM device is communicably coupleable to the memory bus through an NVM device controller, thereby allowing the host processor to access persistent data storable within the NVM device by issuing one or more memory load/store commands to the NVM device controller over the memory bus. Because the NVM device controller includes at least one block window or aperture that defines at least one address range for accessing the persistent data storable within the NVM device, the computer system can exploit the full capacity of the NVM device without being unduly constrained by physical addressing limits imposed by the host processor, or by limits imposed by an operating system executed by the host processor.
摘要翻译：用于访问包括至少一个主处理器和至少一个存储器总线的计算机系统中的非易失性存储器（NVM）设备的装置和方法。 NVM设备通过NVM设备控制器可通信地耦合到存储器总线，从而允许主机处理器通过在存储器总线上向NVM设备控制器发出一个或多个存储器加载/存储命令来访问可存储在NVM设备内的持久数据。因为NVM设备控制器包括至少一个限定了至少一个地址范围的块窗口或孔径，用于访问可存储在NVM设备内的持久数据，所以计算机系统可以利用NVM设备的全部容量，而不会被物理寻址过度约束由主处理器施加的限制，或由主处理器执行的操作系统施加的限制。

18. 发明授权

US07818560B2 System information synchronization in a links-based multi-processor system 有权
标题翻译：基于链路的多处理器系统中的系统信息同步
公开(公告)号：US07818560B2
公开(公告)日：2010-10-19
申请号：US11859640
申请日：2007-09-21
申请人： Yufu Li , XiaoHua Cai , Rahul Khanna , Murugasamy Nachimuthu , Vincent J. Zimmer
发明人： Yufu Li , XiaoHua Cai , Rahul Khanna , Murugasamy Nachimuthu , Vincent J. Zimmer
IPC分类号： G06F15/177
CPC分类号： G06F15/177 , G06F9/4405
摘要： Various embodiments described herein include one or more of systems, methods, firmware, and software to synchronize system information between processors during system boot in a links-based multi-processor system. Some embodiments synchronize data block by block through memory rather than piece by piece through registers by allowing a System Bootstrap Processor (“SBSP”) to directly access synchronization data in local memory of each of one or more Application Processors. These and other embodiments are described in greater detail below.
摘要翻译：本文描述的各种实施例包括在基于链路的多处理器系统中的系统引导期间在处理器之间同步系统信息的系统，方法，固件和软件中的一个或多个。一些实施例通过允许系统引导处理器（“SBSP”）直接访问一个或多个应用处理器中的每一个的本地存储器中的同步数据，通过存储器而不是通过寄存器逐块同步数据。下面更详细地描述这些和其它实施例。

19. 发明授权

US07555671B2 Systems and methods for implementing reliability, availability and serviceability in a computer system 失效
标题翻译：在计算机系统中实现可靠性，可用性和可维护性的系统和方法
公开(公告)号：US07555671B2
公开(公告)日：2009-06-30
申请号：US11513872
申请日：2006-08-31
申请人： Murugasamy Nachimuthu , Singaravelan Nallasellan , Mohan J. Kumar
发明人： Murugasamy Nachimuthu , Singaravelan Nallasellan , Mohan J. Kumar
IPC分类号： G06F11/00
CPC分类号： G06F9/4812
摘要： Embodiments include systems and methods for processing Reliability, Availability and Serviceability (RAS) events in a computer system. Embodiments comprise processing critical events in a first portion of a Management Interrupt (MI) period. The MI period is chosen to be not greater than a maximum tolerable Operating System (OS) latency period. If time remains in a current MI period after processing critical events, the system then processes non-critical events during the time remaining in the current MI period. If at the end of the current MI period, some non-critical events remain to be processed, a subsequent MI period is scheduled to process the remaining non-critical events.
摘要翻译：实施例包括用于处理计算机系统中的可靠性，可用性和可服务性（RAS）事件的系统和方法。实施例包括处理管理中断（MI）周期的第一部分中的关键事件。 MI周期被选择为不大于最大容许的操作系统（OS）等待时间周期。如果在处理关键事件之后的时间内仍处于当前的MI周期，则系统在当前MI周期的剩余时间内处理非关键事件。如果在目前的MI期结束时，一些非关键事件仍然待处理，则随后的MI期间被安排处理剩余的非关键事件。

20. 发明申请

US20090144476A1 HOT PLUG IN A LINK BASED SYSTEM 审中-公开
标题翻译：基于链接的系统中的热插拔
公开(公告)号：US20090144476A1
公开(公告)日：2009-06-04
申请号：US11949970
申请日：2007-12-04
申请人： Xiaohua Cai , Yufu Li , Murugasamy Nachimuthu
发明人： Xiaohua Cai , Yufu Li , Murugasamy Nachimuthu
IPC分类号： G06F13/00
CPC分类号： G06F13/4063
摘要： Machine-readable medium, processes and systems for adding and/or removing components from a running computing device based upon a static topology table and a dynamic topology table are disclosed.
摘要翻译：公开了用于基于静态拓扑表和动态拓扑表从运行的计算设备添加和/或移除组件的机器可读介质，过程和系统。

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