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11. 发明授权

US07644220B2 Programmable controller 有权
标题翻译：可编程控制器
公开(公告)号：US07644220B2
公开(公告)日：2010-01-05
申请号：US12042068
申请日：2008-03-04
申请人： Takao Moriyama , Hideyuki Oguro , Seigo Inobe
发明人： Takao Moriyama , Hideyuki Oguro , Seigo Inobe
IPC分类号： G06F13/36
CPC分类号： G05B19/054 , G05B2219/1144
摘要： In a programmable controller including a special unit, a special-purpose integrated circuit element can be readily utilized for multiple purposes to extend the range of applications to reduce a manufacture cost. A special unit (130) connected to a microprocessor for performing I/O control through a bus includes an integrated circuit element (10) having a logic circuit unit (1000n (n=0 to 7)) whose operation specifications are determined by a parameter memory. The logic circuit unit (1000n) includes a reversible counter used for both high-speed input processing and high-speed output processing as a main component, and is connected to I/O interface circuits (139X) (139Y) through a first port (11) and a second port (12). In addition, because the function of the logic circuit unit (1000n) is determined by a content of a special instruction in a sequential program, the logic circuit unit (1000n) is commonly used for various types of I/O interface circuits to allow the integrated circuit element to be used for multiple purposes.
摘要翻译：在包括特殊单元的可编程控制器中，专用集成电路元件可以容易地用于多个目的以扩展应用范围以降低制造成本。连接到微处理器以通过总线执行I / O控制的特殊单元（130）包括具有逻辑电路单元（1000n（n = 0至7））的集成电路元件（10），其操作规格由参数确定记忆。逻辑电路单元（1000n）包括用于高速输入处理和高速输出处理两者的可逆计数器作为主要组件，并且通过第一端口（I / O接口电路（139Y））连接到I / O接口电路 11）和第二端口（12）。此外，由于逻辑电路单元（1000n）的功能由顺序程序中的特殊指令的内容确定，逻辑电路单元（1000n）通常用于各种类型的I / O接口电路，以允许集成电路元件用于多种用途。

12. 发明申请

US20080196081A1 Switching between unsecure system software and secure system software 失效
标题翻译：在不安全的系统软件和安全系统软件之间切换
公开(公告)号：US20080196081A1
公开(公告)日：2008-08-14
申请号：US11539639
申请日：2006-10-08
申请人： Hassan Hajji , Seiichi Kawano , Takao Moriyama
发明人： Hassan Hajji , Seiichi Kawano , Takao Moriyama
IPC分类号： G06F17/00 , G06F21/00
CPC分类号： G06F21/57 , G06F21/74 , G06F2221/2105
摘要： Unsecure system software and secure system software on the same computer system is switched between. A computer system includes one or more processors, which may not have any built-in security features, memory, and firmware. The memory stores secure system software and unsecure system software. In response to receiving a user signal, the firmware switches from the unsecure system software running on the processors to the secure system software running on the processors (and back again). While the unsecure system software is running, the secure system software is protected from tampering by the unsecure system software.
摘要翻译：在同一计算机系统上的不安全系统软件和安全系统软件之间切换。计算机系统包括一个或多个处理器，其可以不具有任何内置的安全特征，存储器和固件。内存存储安全系统软件和不安全的系统软件。响应于接收到用户信号，固件从在处理器上运行的不安全的系统软件切换到在处理器上运行的安全系统软件（并且再次返回）。当不安全的系统软件正在运行时，安全系统软件将受到不安全的系统软件的篡改的保护。

13. 发明申请

US20070038987A1 PREPROCESSOR TO IMPROVE THE PERFORMANCE OF MESSAGE-PASSING-BASED PARALLEL PROGRAMS ON VIRTUALIZED MULTI-CORE PROCESSORS 失效
标题翻译：提高基于消息传递的并行程序在虚拟化多核处理器上的性能的预处理器
公开(公告)号：US20070038987A1
公开(公告)日：2007-02-15
申请号：US11463496
申请日：2006-08-09
申请人： Moriyoshi Ohara , Yukihiko Sohda , Hiroshi Inoue , Takao Moriyama , Hideaki Komatsu
发明人： Moriyoshi Ohara , Yukihiko Sohda , Hiroshi Inoue , Takao Moriyama , Hideaki Komatsu
IPC分类号： G06F9/45
CPC分类号： G06F8/45
摘要： Provided is a complier which optimizes parallel processing. The complier records the number of execution cores, which is the number of processor cores that execute a target program. First, the compiler detects a dominant path, which is a candidate of an execution path to be consecutively executed by a single processor core, from a target program. Subsequently, the compiler selects dominant paths with the number not larger than the number of execution cores, and generates clusters of tasks to be executed by a multi-core processor in parallel or consecutively. After that, the compiler computes an execution time for which each of the generated clusters is executed by the processor cores with the number equal to one or each of a plurality natural numbers selected from the natural numbers not larger than the number of execution cores. Then, the compiler selects the number of processor cores to be assigned for execution of each of the clusters based on the computed execution time.
摘要翻译：提供了优化并行处理的编译器。编译器记录执行核心数量，即执行目标程序的处理器核心数。首先，编译器从目标程序检测作为由单个处理器核心连续执行的执行路径的候选者的主路径。随后，编译器选择不大于执行核心数量的主导路径，并且并行或连续地生成由多核处理器执行的任务集群。之后，编译器计算执行时间，其中每个生成的集群由处理器核执行，数量等于从不大于执行核心数的自然数中选择的多个自然数中的一个或每个。然后，编译器基于计算出的执行时间选择要分配用于每个簇的执行的处理器核心的数量。

14. 发明授权

US5522060A Multiprocessor memory managing system and method for executing sequentially renewed instructions by locking and alternately reading slave memories 失效
标题翻译：多处理器存储器管理系统和方法，用于通过锁定和交替地读取从属存储器来执行顺序更新的指令
公开(公告)号：US5522060A
公开(公告)日：1996-05-28
申请号：US331291
申请日：1994-10-28
申请人： Kei Kawase , Takashi Matsumoto , Takao Moriyama
发明人： Kei Kawase , Takashi Matsumoto , Takao Moriyama
IPC分类号： G06F13/18 , G06F15/16 , G06F15/177 , G06T1/20 , G06F13/00 , G06F13/14
CPC分类号： G06T1/20
摘要： A multiprocessor memory managing system and method make it possible for a series of instructions corresponding to a data set, which is sequentially renewed by a series of data, to be sequentially executed by a multiprocessor with small overhead. More specifically, the system and method provide a procedure dealing with a data set which is sequentially renewed by a series of data having a sequence, in which snap shots of the data set at arbitrary points of time are assigned to element processors of a multiprocessor at a high speed to execute instructions corresponding to the snap shots in an efficient and parallel fashion. The apparatus includes a master memory and first and second slave memories for storing renewable data. The first and second slave memories are alternately locked and read for snapshots of the renewable data.
摘要翻译：多处理器存储器管理系统和方法使得可以通过一系列数据顺序地更新的一系列与多个处理器以较小开销执行的指令相对应的指令成为可能。更具体地说，系统和方法提供了一种处理数据集的过程，该数据集由具有序列的一系列数据顺序地更新，其中在任意时间点的数据集的快照被分配给多处理器的元素处理器以高效率并行方式执行与快照相对应的指令的高速度。该装置包括主存储器和用于存储可再生数据的第一和第二从属存储器。第一和第二从属存储器交替地锁定并读取可再生数据的快照。

15. 发明授权

US08745414B2 Switching between unsecure system software and secure system software 失效
标题翻译：在不安全的系统软件和安全系统软件之间切换
公开(公告)号：US08745414B2
公开(公告)日：2014-06-03
申请号：US13436893
申请日：2012-03-31
申请人： Hassan Hajji , Seiichi Kawano , Takao Moriyama
发明人： Hassan Hajji , Seiichi Kawano , Takao Moriyama
IPC分类号： G06F21/00 , G06F21/57 , G06F21/74
CPC分类号： G06F21/57 , G06F21/74 , G06F2221/2105
摘要： Unsecure system software and secure system software on the same computer system is switched between. A computer system includes one or more processors, which may not have any built-in security features, memory, and firmware. The memory stores secure system software and unsecure system software. In response to receiving a user signal, the firmware switches from the unsecure system software running on the processors to the secure system software running on the processors (and back again). While the unsecure system software is running, the secure system software is protected from tampering by the unsecure system software.
摘要翻译：在同一计算机系统上的不安全系统软件和安全系统软件之间切换。计算机系统包括一个或多个处理器，其可以不具有任何内置的安全特征，存储器和固件。内存存储安全系统软件和不安全的系统软件。响应于接收到用户信号，固件从在处理器上运行的不安全的系统软件切换到在处理器上运行的安全系统软件（并且再次返回）。当不安全的系统软件正在运行时，安全系统软件将受到不安全的系统软件的篡改的保护。

16. 发明授权

US08291398B2 Compiler for optimizing program 失效
标题翻译：编译器优化程序
公开(公告)号：US08291398B2
公开(公告)日：2012-10-16
申请号：US12259746
申请日：2008-10-28
申请人： Motohiro Kawahito , Hideaki Komatsu , Takao Moriyama
发明人： Motohiro Kawahito , Hideaki Komatsu , Takao Moriyama
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/443 , G06F8/4435
摘要： A compiler system and method for calculating a value to be assigned to a variable for optimizing a program. The apparatus includes a subrange analysis unit for analyzing, for an instruction to assign a value to a variable in the program, a range of the value being assignable to the variable by the instruction, as a subrange of the variable in a case where instruction is executed; a determination unit for determining if the execution result of the program changes if the instruction assigns any value in the subrange of the variable to the variable on the basis of the analyzed subrange of the variable; and a replacement unit for replacing the instruction to assign the value to the variable with an instruction to assign a constant value in the subrange of the variable to the variable.
摘要翻译：用于计算要分配给用于优化程序的变量的值的编译器系统和方法。该装置包括一个子范围分析单元，用于对于在程序中的变量分配值的指令，分析指令中可变量值的范围，作为在指令为执行确定单元，用于如果所述指令基于所分析的所述变量的子范围将所述变量的子范围中的任何值分配给所述变量，则确定所述程序的执行结果是否改变; 以及替换单元，用于用指令将变量的子范围中的常数值分配给变量来替换指定给变量的指令。

17. 发明授权

US07386324B2 System and method for dual path terminal connection 有权
标题翻译：双路终端连接的系统和方法
公开(公告)号：US07386324B2
公开(公告)日：2008-06-10
申请号：US10247950
申请日：2002-09-20
申请人： Takao Moriyama , Kei Kawase
发明人： Takao Moriyama , Kei Kawase
IPC分类号： H04M1/00
CPC分类号： G06F3/14 , G06F3/1415 , G06F3/1454 , G09G2310/04 , G09G2370/04 , G09G2370/045
摘要： For communication between a display device and a processing apparatus (host), two connection modes are prepared, a wired connection mode, for communication along a wired connection path, and a wireless connection mode, for communication along a wireless connection path. Before entering the wireless connection mode, the processing apparatus (host) transmits, along the wired connection path to the display device, data required for the wireless connection of the display device 50 along the wireless connection path, and data required for authentication to permit information to be accessed using the wireless connection path.
摘要翻译：对于显示设备和处理设备（主机）之间的通信，准备两个连接模式，用于沿有线连接路径进行通信的有线连接模式和无线连接模式，用于沿无线连接路径进行通信。在进入无线连接模式之前，处理装置（主机）沿着有线连接路径向显示装置发送显示装置50沿着无线连接路径的无线连接所需的数据，以及认证所需的数据以允许信息使用无线连接路径进行访问。

18. 发明申请

US20070192767A1 Reduced data transfer during processor context switching 失效
标题翻译：在处理器上下文切换期间减少数据传输
公开(公告)号：US20070192767A1
公开(公告)日：2007-08-16
申请号：US11353288
申请日：2006-02-11
申请人： Hiroshi Inoue , Moriyoshi Ohara , Takao Moriyama , Yukihiko Sohda , Hideaki Komatsu
发明人： Hiroshi Inoue , Moriyoshi Ohara , Takao Moriyama , Yukihiko Sohda , Hideaki Komatsu
IPC分类号： G06F9/46
CPC分类号： G06F9/462
摘要： Data transfer during processor context switching is reduced, particularly in relation to a time-sharing microtasking programming model. Prior to switching context of a processor having local memory from a first to a second process, a portion of the local memory that does not require transfer to system memory for proper saving of data associated with the first process is determined. The context of the processor is then switched from the first to the second process, including transferring all of the local memory as the data associated with the first process, to system memory—except for the portion of the local memory that has been determined as not requiring saving to the system memory for proper saving of the data associated with the first process. Therefore, switching the context from the first to the second process results in a reduction of data transferred from the local memory to the system memory.
摘要翻译：处理器上下文切换期间的数据传输减少，特别是在分时微任务编程模型方面。在将具有本地存储器的处理器从第一处理切换到第二处理之前，确定不需要传送到系统存储器以适当地保存与第一处理相关联的数据的本地存储器的一部分。然后，处理器的上下文从第一处理切换到第二处理，包括将与第一处理相关联的所有本地存储器传送到系统存储器 - 除了被确定为不是的本地存储器的部分之外需要保存到系统存储器以适当地保存与第一进程相关联的数据。因此，将上下文从第一处理切换到第二处理导致从本地存储器传送到系统存储器的数据的减少。

19. 发明申请

US20070046505A1 Delimiter lookup using processor permutation instruction 有权
标题翻译：使用处理器置换指令的分隔符查找
公开(公告)号：US20070046505A1
公开(公告)日：2007-03-01
申请号：US11215694
申请日：2005-08-30
申请人： Hiroshi Inoue , Takao Moriyama , Motohiro Kawahito , Hideaki Komatsu
发明人： Hiroshi Inoue , Takao Moriyama , Motohiro Kawahito , Hideaki Komatsu
IPC分类号： H03M7/34
CPC分类号： G06F17/30985
摘要： Delimiter lookup is accomplished using a processor permutation instruction. A 256-bit bitmap is defined and stored within two sixteen-byte registers. Each bit of the bitmap represents an eight-bit character occurrable within a character string, such as a section of eXtensible Markup Language (XML) code, and has a value indicating whether the character is a target character, such as a delimiter. The character string has a number of eight-bit characters at a corresponding number of positions. The first position within the character string at which one of the target characters occurs is determined, using the 256-bit bitmap and a processor permutation instruction. The first position within the character string at which one of the target characters occurs, as has been determined, is output.
摘要翻译：使用处理器排列指令来完成定界符查找。 256位位图被定义并存储在两个十六位寄存器中。位图的每一位表示字符串中可出现的八位字符，例如可扩展标记语言（XML）代码的一部分，并且具有指示字符是否是目标字符（如分隔符）的值。字符串在相应数量的位置具有多个8位字符。使用256位位图和处理器置换指令来确定发生目标字符之一的字符串内的第一位置。输出字符串中出现目标字符之一的第一个位置，如已确定的那样。

20. 发明授权

US5757374A Method and apparatus for performing texture mapping 失效
标题翻译：用于执行纹理映射的方法和装置
公开(公告)号：US5757374A
公开(公告)日：1998-05-26
申请号：US519497
申请日：1995-08-25
申请人： Fusashi Nakamura , Kei Kawase , Takao Moriyama
发明人： Fusashi Nakamura , Kei Kawase , Takao Moriyama
IPC分类号： G06T9/00 , G06T11/20 , G06T15/00 , G06T17/10 , G06T11/00
CPC分类号： G06T17/10
摘要： A computer graphics apparatus connects a texture coordinate generator with fragment generators via a command bus. The generator is connected to a texture data bus through a texture memory cluster which comprises an address generator connected to a texture coordinate bus, a filter, and eight memories. In addition, the generator is connected to the texture data bus through a plurality of texture memory clusters. The texture data bus is connected to a plurality of drawing processors to which a plurality of frame memories are connected in correspondence. This configuration performs texture mapping through effective utilization of the texture memory clusters.
摘要翻译：计算机图形装置通过命令总线连接纹理坐标发生器和碎片生成器。发生器通过纹理存储器簇连接到纹理数据总线，纹理存储器簇包括连接到纹理坐标总线，滤波器和八个存储器的地址发生器。此外，发生器通过多个纹理存储器簇连接到纹理数据总线。纹理数据总线连接到多个绘图处理器，多个帧存储器相应地连接到该绘图处理器。该配置通过有效利用纹理存储器集群来执行纹理映射。

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