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11. 发明申请

US20050106835A1 Trench isolation structure and method of manufacture therefor 审中-公开
标题翻译：沟槽隔离结构及其制造方法
公开(公告)号：US20050106835A1
公开(公告)日：2005-05-19
申请号：US10716278
申请日：2003-11-18
申请人： Nace Layadi , Alvaro Maury
发明人： Nace Layadi , Alvaro Maury
IPC分类号： H01L21/762 , H01L21/8234 , H01L21/76
CPC分类号： H01L21/76224 , H01L21/823481
摘要： The present invention provides a trench isolation structure, a method for manufacturing a trench isolation structure, and a method for manufacturing an integrated circuit including the trench isolation structure. The trench isolation structure, in accordance with the principles of the present invention, may include a substrate having a trench located therein, and an isolation material located within the trench, wherein the isolation material has no undercut at corners where the isolation material meets the substrate.
摘要翻译：本发明提供一种沟槽隔离结构，一种用于制造沟槽隔离结构的方法，以及一种用于制造包括沟槽隔离结构的集成电路的方法。根据本发明的原理，沟槽隔离结构可以包括其中具有沟槽的衬底和位于沟槽内的隔离材料，其中隔离材料在隔离材料与衬底相遇的拐角处没有底切。

12. 发明授权

US06281128B1 Wafer carrier modification for reduced extraction force 有权
标题翻译：晶片载体修改减少提取力
公开(公告)号：US06281128B1
公开(公告)日：2001-08-28
申请号：US09332216
申请日：1999-06-14
申请人： Alvaro Maury , John A. Maze , Frank Miceli , Jose Omar Rodriguez , Robert M. Symons
发明人： Alvaro Maury , John A. Maze , Frank Miceli , Jose Omar Rodriguez , Robert M. Symons
IPC分类号： H01L21302
CPC分类号： B24B37/30
摘要： The present invention provides a wafer carrier for use with a semiconductor wafer polishing apparatus. In one embodiment, the wafer carrier comprises a carrying head having opposing first and second surfaces, a primary channel system formed in the second surface, and a secondary channel system formed in the second surface. The first surface is coupleable to the semiconductor polishing apparatus and the second surface is adapted to receive a semiconductor wafer to be polished. The primary channel system comprises first and second intersecting channels. The secondary channel system intersects the primary channel system so that the secondary channel system and the primary channel system cooperate to occupy a substantial portion of a surface area of the second surface. Therefore, the primary channel system and the secondary channel system decrease an amount of force required to remove the semiconductor wafer from the second surface.
摘要翻译：本发明提供一种与半导体晶片抛光装置一起使用的晶片载体。在一个实施例中，晶片载体包括具有相对的第一和第二表面的承载头，形成在第二表面中的主要通道系统，以及形成在第二表面中的辅助通道系统。第一表面可耦合到半导体抛光装置，第二表面适于接收待抛光的半导体晶片。主通道系统包括第一和第二相交通道。次通道系统与主通道系统相交，使得辅助通道系统和主通道系统协同占据第二表面的表面区域的主要部分。因此，主通道系统和次通道系统减少了从第二表面移除半导体晶片所需的力。

13. 发明授权

US6110012A Chemical-mechanical polishing apparatus and method 有权
标题翻译：化学机械抛光装置及方法
公开(公告)号：US6110012A
公开(公告)日：2000-08-29
申请号：US220417
申请日：1998-12-24
申请人： Alvaro Maury , Arun Kumar Nanda , Jose Omar Rodriguez
发明人： Alvaro Maury , Arun Kumar Nanda , Jose Omar Rodriguez
IPC分类号： H01L21/302 , B24B37/32 , B24B57/02 , H01L21/304 , B24B1/00 , B24B29/00
CPC分类号： B24B37/32 , B24B57/02
摘要： A method and apparatus for limiting or eliminating the edge effect in a chemical mechanical polishing apparatus comprising a substrate holder and a retaining ring spaced from and around the holder, a rotatable platen and a polishing pad on the platen, by essentially flattening the pad in the area in which it normally tends to deform. The invention is carried out by applying a fluid under pressure, preferably the polishing slurry, to the pad in the region of the gap between the retaining ring and the holder to substantially flatten the pad in the area around the edge of the substrate.
摘要翻译：一种用于限制或消除化学机械抛光装置中的边缘效应的方法和装置，其包括基板保持器和保持器间隔开并围绕保持器的可移动压板和抛光垫，通过使垫其通常倾向于变形的区域。本发明通过将压力下的流体（优选抛光浆料）施加到保持环和保持器之间的间隙区域中的垫上，以在基板边缘周围的区域中使焊盘基本上平坦化。

14. 发明授权

US07811944B2 Semiconductor device and a method of manufacture therefor 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07811944B2
公开(公告)日：2010-10-12
申请号：US11167772
申请日：2005-06-27
申请人： Nace Rossi , Alvaro Maury
发明人： Nace Rossi , Alvaro Maury
IPC分类号： H01L21/31
CPC分类号： H01L23/53295 , C23C16/401 , H01L21/02131 , H01L21/02274 , H01L21/02362 , H01L21/31612 , H01L21/76801 , H01L21/76832 , H01L21/823871 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the aforementioned semiconductor device. The semiconductor device, in accordance with the principles of the present invention, may include a substrate, and a graded capping layer located over the substrate, wherein the graded capping layer includes at least two different layers, wherein first and second layers of the at least two different layers have different stress values.
摘要翻译：本发明提供一种半导体器件及其制造方法以及包括上述半导体器件的集成电路。根据本发明的原理，半导体器件可以包括衬底和位于衬底上的分级覆盖层，其中分级覆盖层包括至少两个不同的层，其中至少第二层和第二层两个不同的层具有不同的应力值。

15. 发明申请

US20050277372A1 Zone polishing using variable slurry solid content 有权
公开(公告)号：US20050277372A1
公开(公告)日：2005-12-15
申请号：US11208829
申请日：2005-08-22
申请人： Alvaro Maury , Jovin Lim , Nace Layadi , Sebastian Ouek
发明人： Alvaro Maury , Jovin Lim , Nace Layadi , Sebastian Ouek
IPC分类号： B24B37/04 , B24B57/02 , B24B1/00
CPC分类号： B24B37/04 , B24B57/02
摘要： A slurry dispensing apparatus for use with a chemical mechanical polishing tool for planarizing semiconductor substrates having irregular topology. The apparatus includes a slurry dispensing manifold with a first end suspended over a polishing pad, and a second end for mounting to the chemical mechanical polishing tool. The slurry dispensing manifold has a linear array of nozzles positioned under the suspended manifold. Each nozzle provides an adjusted slurry mixture that is supplied from bifurcated supply lines. A first branch supplying a slurry, and a second branch supplying deionized water. Each nozzle is capable of providing a particular slurry concentration to either decrease or to increase polishing rate in specific zonal areas on a substrate according to its surface topology.

16. 发明申请

US20050106919A1 CONTACT FOR USE IN AN INTEGRATED CIRCUIT AND A METHOD OF MANUFACTURE THEREFOR 失效
标题翻译：联系用于集成电路及其制造方法
公开(公告)号：US20050106919A1
公开(公告)日：2005-05-19
申请号：US10716299
申请日：2003-11-18
申请人： Nace Layadi , Alvaro Maury
发明人： Nace Layadi , Alvaro Maury
IPC分类号： H01L21/768 , H01R13/28 , H01R25/00
CPC分类号： H01L21/76877
摘要： The present invention provides a contact for use in an integrated circuit, a method of manufacture therefor, and an integrated circuit including the aforementioned contact. The contact, in accordance with the principles of the present invention, may include a via located in a substrate, and a contact plug located in the via, wherein the contact plug has a first portion having a notch removed therefrom and a second portion filling the notch.
摘要翻译：本发明提供了一种用于集成电路的接点及其制造方法，以及包括上述接触的集成电路。根据本发明的原理的触点可以包括位于基板中的通孔和位于通孔中的接触塞，其中接触插塞具有从其中移除的凹口的第一部分和填充该通孔的第二部分缺口。

17. 发明申请

US20050026549A1 Zone polishing using variable slurry solid content 失效
标题翻译：使用可变浆料固体含量进行区域抛光
公开(公告)号：US20050026549A1
公开(公告)日：2005-02-03
申请号：US10633131
申请日：2003-08-01
申请人： Alvaro Maury , Jovin Lim , Nace Layadi , Sebastian Quek
发明人： Alvaro Maury , Jovin Lim , Nace Layadi , Sebastian Quek
IPC分类号： B24B37/04 , B24B57/02 , B24B49/00 , B24B51/00
CPC分类号： B24B37/04 , B24B57/02
摘要： A slurry dispensing apparatus for use with a chemical mechanical polishing tool for planarizing semiconductor substrates having irregular topology. The apparatus includes a slurry dispensing manifold with a first end suspended over a polishing pad, and a second end for mounting to the chemical mechanical polishing tool. The slurry dispensing manifold has a linear array of nozzles positioned under the suspended manifold. Each nozzle provides an adjusted slurry mixture that is supplied from bifurcated supply lines. A first branch supplying a slurry, and a second branch supplying deionized water. Each nozzle is capable of providing a particular slurry concentration to either decrease or to increase polishing rate in specific zonal areas on a substrate according to its surface topology.
摘要翻译：一种用于与化学机械抛光工具一起用于平坦化具有不规则拓扑的半导体衬底的浆料分配装置。该设备包括具有悬挂在抛光垫上的第一端的浆料分配歧管和用于安装到化学机械抛光工具的第二端。浆料分配歧管具有位于悬浮歧管下方的线性阵列的喷嘴。每个喷嘴提供从分叉供应管线供应的经调节的浆料混合物。供应浆料的第一分支和供应去离子水的第二分支。根据其表面拓扑结构，每个喷嘴能够提供特定的浆料浓度以降低或提高基材上特定区带区域的抛光速率。

18. 发明授权

US06821886B1 IMP TiN barrier metal process 失效
标题翻译： IMP TiN阻挡金属工艺
公开(公告)号：US06821886B1
公开(公告)日：2004-11-23
申请号：US10655690
申请日：2003-09-05
申请人： Nace Layadi , Alvaro Maury , Jovin Lim
发明人： Nace Layadi , Alvaro Maury , Jovin Lim
IPC分类号： H01L2144
CPC分类号： H01L21/76846 , H01L21/76805 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： A new method is provided for the creation of an adhesion/barrier layer over which a tungsten interconnect is created. The invention reduces metal extrusion and effects of pin-holes by dividing the process of barrier material of TiN deposition into phases, whereby after about half the thickness of the required layer of TiN has been deposited, an intermediate and very thin layer of Ti is deposited. After the thin layer of Ti has been deposited, the deposition of the barrier layer of TiN is continued to the point where the required thickness for the layer of TiN has been reached.
摘要翻译：提供了一种新的方法来创建粘附/阻挡层，在其上形成钨互连。本发明通过将TiN沉积的阻挡材料的工艺分成相来减少金属挤出和针孔的影响，由此在所需的TiN层的厚度的大约一半已经沉积之后，沉积中间层和非常薄的Ti层。在沉积薄层的Ti之后，TiN阻挡层的沉积继续到达到TiN层所需厚度的程度。

19. 发明授权

US06309900B1 Test structures for testing planarization systems and methods for using same 有权
标题翻译：用于测试平面化系统的测试结构及其使用方法
公开(公告)号：US06309900B1
公开(公告)日：2001-10-30
申请号：US09480387
申请日：2000-01-11
申请人： Alvaro Maury , Frank Miceli , Subramanian Karthikeyan
发明人： Alvaro Maury , Frank Miceli , Subramanian Karthikeyan
IPC分类号： H01L2166
CPC分类号： H01L22/34
摘要： Test structures are disclosed for use in a system and with an associated method to test the effectiveness of planarization systems used in the fabrication of semiconductor devices and integrated circuits. A method of creating the test structure utilizes traditional semiconductor fabrication techniques, but uses substantially similar materials, such as oxide, for each of the layers of the test structure. Because the test structure comprises layers of substantially the same material, reliable uniform measurements of the thickness of the test structure may be obtained by an optical metrology tool. These measurements may then be analyzed and displayed in tabular reports or multi-dimensional plots to judge the effectiveness of the planarization system.
摘要翻译：公开了用于系统中的测试结构以及用于测试在半导体器件和集成电路的制造中使用的平面化系统的有效性的相关方法。创建测试结构的方法利用传统的半导体制造技术，但是对测试结构的每个层使用基本相似的材料，例如氧化物。由于测试结构包括基本上相同材料的层，所以通过光学测量工具可以获得测试结构的厚度的可靠的均匀测量。然后可以将这些测量结果分析并显示在表格报告或多维图中，以判断平面化系统的有效性。

20. 发明授权

US06261958B1 Method for performing chemical-mechanical polishing 有权
标题翻译：化学机械抛光方法
公开(公告)号：US06261958B1
公开(公告)日：2001-07-17
申请号：US09450485
申请日：1999-11-29
申请人： Annette Margaret Crevasse , Alvaro Maury , Sanjay Patel , John Thomas Sowell
发明人： Annette Margaret Crevasse , Alvaro Maury , Sanjay Patel , John Thomas Sowell
IPC分类号： H01L21302
CPC分类号： B24B37/11 , B24B45/00
摘要： An apparatus and method for performing chemical-mechanical polishing is disclosed in which the pad is secured to the platen without the use of adhesives. A polishing pad and a platen are secured together by a releasable attractive force; the force may comprise a vacuum or electromagnetic force, and the pad has a hard or magnetic backside layer for facing the plating and responding to the attractive force. This invention has particular application to chemical-mechanical polishing for use in planarizing dielectrics.
摘要翻译：公开了一种用于进行化学机械抛光的装置和方法，其中垫不用粘合剂固定在压板上。抛光垫和压板通过可释放的吸引力固定在一起; 力可以包括真空或电磁力，并且垫具有用于面对镀层并响应于吸引力的硬或磁性背面层。本发明特别适用于平面化电介质中使用的化学机械抛光。

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