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11. 发明授权

US09147419B2 Generating position error signal based on data tracks for magnetic data storage 有权
标题翻译：根据磁数据存储的数据轨迹生成位置误差信号
公开(公告)号：US09147419B2
公开(公告)日：2015-09-29
申请号：US14499819
申请日：2014-09-29
申请人： Marvell World Trade Ltd.
发明人： Mats Oberg , Gregory Burd
IPC分类号： G11B5/596 , G11B20/10 , G11B5/55
CPC分类号： G11B5/59622 , G11B5/5547 , G11B5/59611 , G11B5/59627 , G11B5/5965 , G11B20/10212 , G11B20/10305
摘要： A hard disk drive circuit includes first and second inter-track interference detection modules. The first inter-track interference detection module is configured to generate a first measured inter-track interference value based on a first read signal from a first read sensor positioned over a magnetic medium. The second inter-track interference detection module is configured to generate a second measured inter-track interference value based on a second read signal from a second read sensor positioned over the magnetic medium. A position error signal generation module is configured to generate a position error signal based on the first measured inter-track interference value and the second measured inter-track interference value. An arm control module is configured to control rotation of an arm in response to the position error signal. The first read sensor and the second read sensor are located at a distal end of the arm.
摘要翻译：硬盘驱动电路包括第一和第二轨道间干扰检测模块。第一轨道间干扰检测模块被配置为基于位于磁介质上的第一读取传感器的第一读取信号产生第一测量的轨道间干扰值。第二轨道间干扰检测模块被配置为基于位于磁介质上的第二读取传感器的第二读取信号产生第二测量的轨道间干扰值。位置误差信号生成模块被配置为基于第一测量的轨道间干扰值和第二测量的轨道间干扰值来产生位置误差信号。臂控制模块被配置为响应于位置误差信号来控制臂的旋转。第一读取传感器和第二读取传感器位于臂的远端。

12. 发明申请

US20150092296A1 METHOD AND APPARATUS FOR DETERMINING POSITION OF MULTIPLE DRIVE HEADS 有权
标题翻译：用于确定多个驱动头的位置的方法和装置
公开(公告)号：US20150092296A1
公开(公告)日：2015-04-02
申请号：US14482124
申请日：2014-09-10
申请人： Marvell World Trade Ltd.
发明人： Mats Oberg , Qiyue Zou , Gregory Burd
IPC分类号： G11B5/596
CPC分类号： G11B5/59627 , G11B5/4886 , G11B5/553 , G11B5/59683
摘要： Determining the radial position of a first read head of a storage device includes reading servo data from a storage media platter surface using the first read head, deriving from that servo data a first positron error signal representing a first estimate of the radial position of the first read head, reading the servo data from the storage media platter surface using a different read head, deriving from that servo data a second position error signal representing an estimate of the radial position of the different read head, and combining the first estimate of the radial position of the first read head and the estimate of the radial position of the different read head to obtain a revised estimate of the radial position of the first read head. The combining could include taking account of a known positional offset between the first read head and the different read head.
摘要翻译：确定存储设备的第一读取头的径向位置包括使用第一读取头从存储媒体盘片表面读取伺服数据，从该伺服数据中导出表示第一和第二读取头的径向位置的第一估计的第一正电子误差信号读取头，使用不同的读取头从存储介质盘表面读取伺服数据，从该伺服数据导出表示不同读取头的径向位置的估计的第二位置误差信号，并组合径向的第一估计第一读取头的位置和不同读取头的径向位置的估计，以获得第一读取头的径向位置的修正估计。组合可以包括考虑第一读头和不同读头之间的已知位置偏移。

13. 发明申请

US20140237287A1 IMPLEMENTING RAID IN SOLID STATE MEMORY 有权
标题翻译：在固态存储器中实现RAID
公开(公告)号：US20140237287A1
公开(公告)日：2014-08-21
申请号：US14260237
申请日：2014-04-23
申请人： Marvell World Trade Ltd.
发明人： Gregory Burd
IPC分类号： G06F11/10 , G11C29/52
CPC分类号： G06F11/108 , G06F11/1008 , G06F11/1028 , G06F11/1048 , G06F12/0246 , G06F2212/1032 , G06F2212/7208 , G11C29/52
摘要： The present disclosure includes systems and techniques relating to implementing fault tolerant data storage in solid state memory. In some implementations, a method includes receiving a data request for a solid state memory; identifying a logical block grouping corresponding to the data request, wherein the logical block grouping indicates physical data storage blocks spanning at least two distinct memory units of the solid state memory; reading stored data and parity information from at least a portion of the physical data storage blocks spanning the at least two distinct memory units; and recovering data of at least one block of the logical block grouping based on the stored data and the parity information.
摘要翻译：本公开包括与在固态存储器中实现容错数据存储有关的系统和技术。在一些实现中，一种方法包括接收对固态存储器的数据请求; 识别对应于所述数据请求的逻辑块分组，其中所述逻辑块分组指示跨越所述固态存储器的至少两个不同存储器单元的物理数据存储块; 从跨越至少两个不同存储器单元的物理数据存储块的至少一部分读取存储的数据和奇偶校验信息; 以及基于所存储的数据和所述奇偶校验信息来恢复所述逻辑块分组的至少一个块的数据。

14. 发明申请

US20140160855A1 SYSTEMS AND METHODS FOR GENERATING SOFT INFORMATION IN NAND FLASH 审中-公开
标题翻译：用于在NAND闪存中生成软信息的系统和方法
公开(公告)号：US20140160855A1
公开(公告)日：2014-06-12
申请号：US14177609
申请日：2014-02-11
申请人： Marvell World Trade Ltd.
发明人： Zhengang Chen , Gregory Burd , Shashi Kiran Chilappagari , Xueshi Yang
IPC分类号： G11C16/06 , G11C16/26
CPC分类号： G11C16/06 , G06F11/1048 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/34 , G11C16/3427
摘要： Systems and methods are provided to generate soft information related to the threshold voltage of a memory cell. A range of threshold voltages for the memory cell is divided into subregions of threshold voltage values herein referred to as bins. An output of the memory cell in response to an applied reference signal is measured. The applied reference signal includes a voltage value and position information. A single bin is identified based on the position information of the reference signal. The identified bin is split into more than one bin based on the output of the memory cell and the voltage value of the reference signal. The newly split bins and all the other bins that were not split are assigned new bin indices.
摘要翻译：提供系统和方法以产生与存储器单元的阈值电压相关的软信息。用于存储器单元的阈值电压的范围被划分为这里称为仓的阈值电压值的子区域。测量响应于所施加的参考信号的存储单元的输出。所施加的参考信号包括电压值和位置信息。基于参考信号的位置信息来识别单个箱。基于存储单元的输出和参考信号的电压值，将识别的箱分成多于一个箱。新拆分的箱体以及未分割的所有其他箱体被分配新的箱子索引。

15. 发明授权

US09467170B2 NAND flash memory systems with efficient soft information interface 有权
标题翻译： NAND闪存系统具有高效的软信息接口
公开(公告)号：US09467170B2
公开(公告)日：2016-10-11
申请号：US14267307
申请日：2014-05-01
申请人： Marvell World Trade LTD.
发明人： Shashi Kiran Chilappagari , Gregory Burd
IPC分类号： H03M13/11 , H03M13/37 , H03M13/29 , H03M13/41 , H03M13/45 , H03M13/39 , G11C29/52 , G06F11/10 , H03M13/00
CPC分类号： H03M13/1111 , G06F11/1012 , G06F11/1048 , G06F11/1068 , G11C29/52 , H03M13/1105 , H03M13/1108 , H03M13/2927 , H03M13/2957 , H03M13/2975 , H03M13/3707 , H03M13/3738 , H03M13/3746 , H03M13/3927 , H03M13/41 , H03M13/45 , H03M13/458 , H03M13/6513
摘要： A controller for a nonvolatile memory device includes a transfer control module and a decoder module. The transfer control module is configured to request a read of data from a flash memory module. The data to be read includes data corresponding to a first codeword. The transfer control module is configured to receive hard decisions corresponding to the first codeword from the flash memory module. The transfer control module is configured to receive soft information corresponding to the first codeword from the flash memory module. Both the hard decisions corresponding to the first codeword and the soft information corresponding to the first codeword are received without receiving any intervening hard decisions or soft information corresponding to another codeword. The decoder module is configured to decode the first codeword using the hard decisions and the soft information corresponding to the first codeword.
摘要翻译：非易失性存储器件的控制器包括转移控制模块和解码器模块。转移控制模块被配置为请求从闪存模块读取数据。要读取的数据包括对应于第一码字的数据。传送控制模块被配置为从闪存模块接收对应于第一码字的硬判决。传送控制模块被配置为从闪存模块接收对应于第一码字的软信息。接收对应于第一码字的硬判决和对应于第一码字的软信息，而不接收与另一码字对应的任何介入的硬判决或软信息。解码器模块被配置为使用硬判决和对应于第一码字的软信息来解码第一码字。

16. 发明授权

US09003267B2 Power consumption in LDPC decoder for low-power applications 有权
标题翻译：用于低功耗应用的LDPC解码器中的功耗
公开(公告)号：US09003267B2
公开(公告)日：2015-04-07
申请号：US13868705
申请日：2013-04-23
申请人： Marvell World Trade Ltd.
发明人： Nedeljko Varnica , Gregory Burd
IPC分类号： H03M13/00 , H03M13/13 , H03M13/11 , H03M13/37 , H04L1/00
CPC分类号： H03M13/13 , H03M13/112 , H03M13/1128 , H03M13/114 , H03M13/116 , H03M13/3715 , H03M13/6502 , H04L1/0051 , H04L1/0053 , H04L1/0057
摘要： This disclosure relates generally to low power data decoding, and more particularly to low power iterative decoders for data encoded with a low-density parity check (LDPC) encoder. Systems and methods are disclosed in which a low-power syndrome check may be performed in the first iteration or part of the first iteration during the process of decoding a LDPC code in an LDPC decoder. Systems and methods are also disclosed in which a control over the precision of messages sent or received and/or a change in the scaling of these messages may be implemented in the LDPC decoder. The low-power techniques described herein may reduce power consumption without a substantial decrease in performance of the applications that make use of LDPC codes or the devices that make use of low-power LDPC decoders.
摘要翻译：本公开一般涉及低功率数据解码，更具体地涉及用于利用低密度奇偶校验（LDPC）编码器编码的数据的低功率迭代解码器。公开了一种系统和方法，其中在LDPC解码器中对LDPC码进行解码的过程中，可以在第一次迭代或第一次迭代的一部分中执行低功率综合检查。还公开了系统和方法，其中可以在LDPC解码器中实现对发送或接收的消息的精度的控制和/或这些消息的缩放的改变。本文描述的低功率技术可以降低功耗，而不会大大降低利用LDPC码的应用的性能或者利用低功率LDPC解码器的设备。

17. 发明授权

US08806299B2 Method and apparatus for compressing data sectors in storage drive 有权
标题翻译：用于压缩存储驱动器中的数据扇区的方法和装置
公开(公告)号：US08806299B2
公开(公告)日：2014-08-12
申请号：US13849882
申请日：2013-03-25
申请人： Marvell World Trade Ltd.
发明人： Gregory Burd , Xueshi Yang
IPC分类号： G11C29/00
CPC分类号： G06F12/0238 , G06F3/0608 , G06F3/0611 , G06F3/0616 , G06F3/0619 , G06F3/0623 , G06F3/064 , G06F3/0658 , G06F3/0679
摘要： A storage drive includes a non-volatile semiconductor memory, and interface, a compression module, a sector module, and a control module. The interface is configured to receive first data sectors transmitted from a host to the storage drive. The compression module is configured to compress the first data sectors to generate second data sectors. Lengths of the second data sectors vary. The first sector module is configured to generate third data sectors by adding nuisance data to (i) the second data sectors, or (ii) an encrypted version of the second data sectors, wherein lengths of the third data sectors do not vary. The control module is configured to store the third data sectors in the non-volatile semiconductor memory.
摘要翻译：存储驱动器包括非易失性半导体存储器和接口，压缩模块，扇区模块和控制模块。接口被配置为接收从主机传输到存储驱动器的第一数据扇区。压缩模块被配置为压缩第一数据扇区以产生第二数据扇区。第二个数据扇区的长度变化。第一扇区模块被配置为通过向（i）第二数据扇区添加有害数据或（ii）第二数据扇区的加密版本来生成第三数据扇区，其中第三数据扇区的长度不变。控制模块被配置为将第三数据扇区存储在非易失性半导体存储器中。

18. 发明申请

US20140143641A1 ITERATIVE DECODER SYSTEMS AND METHODS 审中-公开
标题翻译：迭代解码器系统和方法
公开(公告)号：US20140143641A1
公开(公告)日：2014-05-22
申请号：US14166428
申请日：2014-01-28
申请人： Marvell World Trade Ltd.
发明人： Panu Chaichanavong , Nedeljko Varnica , Nitin Nangare , Gregory Burd , Zining Wu
IPC分类号： H03M13/41
CPC分类号： H03M13/41 , G11B20/1426 , G11B20/1803 , G11B2020/10759 , G11B2020/1457 , H03M13/09 , H03M13/1105 , H03M13/1111 , H03M13/1114 , H03M13/13 , H03M13/29 , H03M13/2948 , H03M13/3746 , H03M13/4146 , H03M13/6343 , H03M13/6502 , H03M13/6561
摘要： Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. A 1/(1+D) precoder that may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.
摘要翻译：提供了系统和方法，用于改进迭代解码器系统的设计和性能。在一些实施例中，迭代解码器可以通过FIR RAM从FIR样本去耦，从而导致较不复杂的设计和较短的处理时间。在一些实施例中，当在迭代解码器的SOVA和LDPC之间传递信息时，可以使用中间存储器。在一些实施例中，可以在每次LDPC迭代期间从从LDPC接收的信息中连续序列化所需的SOVA信息。在一些实施例中，HR RLL编码器的1 /（1 + D2）预编码器可以被分成两个串行，1 /（1 + D）个预编码器。一个1 /（1 + D）预编码器可以被拉出HR RLL编码器外部并与迭代解码器结合使用。 1 /（1 + D）预编码器，其可以与迭代解码器一起使用，同时保持由HR RLL编码器施加在编码信息上的RLL约束。

19. 发明申请

US20140002918A1 SYSTEMS AND METHODS FOR READING AND DECODING ENCODED DATA FROM A STORAGE DEVICE 审中-公开
标题翻译：用于从存储设备读取和解码编码数据的系统和方法
公开(公告)号：US20140002918A1
公开(公告)日：2014-01-02
申请号：US13915858
申请日：2013-06-12
申请人： Marvell World Trade Ltd.
发明人： Hongying Sheng , Panu Chaichanavong , Gregory Burd
IPC分类号： G11B20/12
CPC分类号： G11B20/1217 , G11B20/1426 , G11B2220/2516
摘要： Systems and methods of reading data from a storage device are provided. A first codeword and a second codeword are read from a storage device, where the second codeword is positioned after the first codeword. The first and second codewords are decoded in parallel, and the decoding of the second codeword completes before the decoding of the first codeword completes. The decoded second codeword and a signal indicating whether the decoding of the second codeword is complete are transmitted to control circuitry before the decoding of the first codeword completes.
摘要翻译：提供了从存储设备读取数据的系统和方法。从存储设备读取第一码字和第二码字，其中第二码字位于第一码字之后。第一和第二码字被并行解码，第二码字的解码在第一码字的解码完成之前完成。解码的第二码字和指示第二码字的解码是否完整的信号在第一码字的解码完成之前被发送到控制电路。

20. 发明授权

US10255944B2 Systems and methods for reading and decoding encoded data from a storage device 有权
公开(公告)号：US10255944B2
公开(公告)日：2019-04-09
申请号：US13915858
申请日：2013-06-12
申请人： Marvell World Trade Ltd.
发明人： Hongying Sheng , Panu Chaichanavong , Gregory Burd
IPC分类号： G06F13/12 , G06F13/28 , G11B20/12 , G11B20/14
摘要： Systems and methods of reading data from a storage device are provided. A first codeword and a second codeword are read from a storage device, where the second codeword is positioned after the first codeword. The first and second codewords are decoded in parallel, and the decoding of the second codeword completes before the decoding of the first codeword completes. The decoded second codeword and a signal indicating whether the decoding of the second codeword is complete are transmitted to control circuitry before the decoding of the first codeword completes.

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