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11. 发明申请

US20130194923A1 CONVERGED ENHANCED ETHERNET NETWORK 有权
公开(公告)号：US20130194923A1
公开(公告)日：2013-08-01
申请号：US13360679
申请日：2012-01-28
申请人： Claude Basso , Rolf Clauberg , Casimer M. DeCusatis , Mircea Gusat , Ronald P. Luijten , Fredy D. Neeser , Kenneth M. Valk
发明人： Claude Basso , Rolf Clauberg , Casimer M. DeCusatis , Mircea Gusat , Ronald P. Luijten , Fredy D. Neeser , Kenneth M. Valk
IPC分类号： H04L12/26
CPC分类号： H04L43/00 , H04L43/08 , H04L47/30 , H04L47/56
摘要： A system to improve a Converged Enhanced Ethernet network may include a controller having a computer processor connected to a layer 2 endpoint buffer. The system may also include a manager executing on the controller to monitor the layer 2 endpoint buffer by determining buffer data packet occupancy and/or rate of change in the buffer data packet occupancy. The system may further include a reporter to notify a congestion source of the layer 2 endpoint buffer based upon the buffer data packet occupancy and/or rate of change in the buffer data packet occupancy.

12. 发明申请

US20110145545A1 COMPUTER-IMPLEMENTED METHOD OF PROCESSING RESOURCE MANAGEMENT 有权
标题翻译：计算机实施资源管理方法
公开(公告)号：US20110145545A1
公开(公告)日：2011-06-16
申请号：US12635544
申请日：2009-12-10
申请人： Hillery C. Hunter , Ronald P. Luijten , Phillip Stanley-Marbell
发明人： Hillery C. Hunter , Ronald P. Luijten , Phillip Stanley-Marbell
IPC分类号： G06F9/38 , G06F15/76 , G06F9/06
CPC分类号： G06F9/4856 , G06F9/5033 , G06F2212/271
摘要： A computer-implemented method for managing processing resources of a computerized system having at least a first processor and a second processor, each of the processors operatively interconnected to a memory storing a set of data to be processed by a processor, the method comprising: monitoring data accessed by the first processor while executing; and if the second processor is at a shorter distance than the first processor from the monitored data, instructing to interrupt execution at the first processor and resume the execution at the second processor.
摘要翻译：一种用于管理具有至少第一处理器和第二处理器的计算机化系统的处理资源的计算机实现的方法，每个处理器可操作地互连到存储要由处理器处理的一组数据的存储器，所述方法包括：监视在执行时由第一处理器访问的数据; 并且如果所述第二处理器距所述监视数据的距离小于所述第一处理器，则指示中断所述第一处理器处的执行并在所述第二处理器恢复执行。

13. 发明授权

US07103050B1 Method and means for determining the used bandwidth on a connection 失效
标题翻译：用于确定连接上使用的带宽的方法和装置
公开(公告)号：US07103050B1
公开(公告)日：2006-09-05
申请号：US09202365
申请日：1997-04-10
申请人： Ronald P. Luijten , Ken V. Vu
发明人： Ronald P. Luijten , Ken V. Vu
IPC分类号： H04L12/56
CPC分类号： H04L12/5602 , H04L2012/5636 , H04Q11/0478
摘要： The invention relates to a method for determining the used bandwidth (CCR) on a connection (18) on which information-carrying units are transported. The duration (ET) of an arrival period, during which a predetermined number (M) of the cells arrives at a certain point of the connection (18), is measured and stored. The bandwidth (CCR) at an arbitrary point of time (GT) is set to the predetermined number (M) per the stored duration (ET), if the point of time (TS) when the duration (ET) was stored is not longer ago than a predetermined threshold time interval (THR) at the arbitrary point of time (GT).
摘要翻译：本发明涉及一种用于确定在其上传送信息携带单元的连接（18）上的使用带宽（CCR）的方法。测量并存储到达周期的持续时间（ET），在该期间中，预定数量（M）的单元到达连接（18）的某一点。如果存储持续时间（ET）的时间点（TS）不长于，则任意时间点（GT）的带宽（CCR）被设置为每个存储持续时间（ET）的预定数量（M）以前在任意时间点（GT）的预定阈值时间间隔（THR）。

14. 发明授权

US06674716B1 Cell compliance decision method and apparatus 失效
标题翻译：细胞依从性决定方法和装置
公开(公告)号：US06674716B1
公开(公告)日：2004-01-06
申请号：US09381058
申请日：1999-09-13
申请人： Ronald P. Luijten
发明人： Ronald P. Luijten
IPC分类号： H04J314
CPC分类号： H04L12/5602 , H04L49/3081 , H04L2012/5636 , H04Q11/0478
摘要： A method for deciding over the compliance of cells at an input of a switch. The time is counted with a time-counting device with a predetermined maximum counting range for determining the points in time of the arrival of the cells. The reading of the time-counting device is used to determine for a first arriving cell a first arrival time and for a second arriving cell a second arrival time. The second arrival time is compared with a theoretical arrival time for the second cell. The theoretical arrival time is calculated using the first arrival time and a predetermined value of an interarrival period. The number of wraps of the time-counting device is counted. The reading of a wrap-counting device at the second arrival time and at the theoretical arrival time is used to determine whether to use the comparison for deciding whether to consider the second arriving cell compliant or non-compliant or whether to consider the second arriving cell compliant or non-compliant without performing the comparison.
摘要翻译：一种用于决定在开关的输入端上的单元的顺应性的方法。用具有预定的最大计数范围的计时装置计算时间，以确定小区到达时间点。时间计数装置的读取用于确定第一到达小区的第一到达时间，以及对第二到达小区确定第二到达时间。将第二到达时间与第二小区的理论到达时间进行比较。理论到达时间是使用第一到达时间和预期期间的预定值来计算的。对计时装置的包装数进行计数。在第二到达时间和理论到达时间读取包裹计数装置用于确定是否使用比较来确定是否考虑到符合第二个到达的小区或不兼容或是否考虑第二个到达的小区兼容或不符合，而不执行比较。

15. 发明申请

US20130019108A1 ADDRESS TRANSLATION UNIT, DEVICE AND METHOD FOR REMOTE DIRECT MEMORY ACCESS OF A MEMORY 有权
标题翻译：地址转换单元，用于远程存储器的直接存储器访问的设备和方法
公开(公告)号：US20130019108A1
公开(公告)日：2013-01-17
申请号：US13617942
申请日：2012-09-14
申请人： Florian A. Auernhammer , Nikolaos Chrysos , Rolf Clauberg , Andreas C. Doering , Ronald P. Luijten , Patricia M. Sagmeister
发明人： Florian A. Auernhammer , Nikolaos Chrysos , Rolf Clauberg , Andreas C. Doering , Ronald P. Luijten , Patricia M. Sagmeister
IPC分类号： G06F12/14 , G06F21/00
CPC分类号： G06F12/1081 , G06F12/1408 , H04L9/00 , H04L9/0894 , H04L9/3247 , Y02D10/13
摘要： A method for Remote Direct Memory Access (RDMA) of a memory of a processor. An address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address.
摘要翻译：一种用于处理器存储器的远程直接存储器访问（RDMA）的方法。地址转换单元包括地址转换器和签名者。地址转换器被配置为在存储器的实际地址中转换接收的虚拟地址。签名者被配置为对真实地址进行加密签名。

16. 发明申请

US20080165793A1 MEMORY SHARING MECHANISM BASED ON PRIORITY ELEVATION 失效
标题翻译：基于优先级的记忆共享机制
公开(公告)号：US20080165793A1
公开(公告)日：2008-07-10
申请号：US12051177
申请日：2008-03-19
申请人： Francois G. Abel , Wolfgang Denzel , Antonius Engbersen , Ferdinand Gramsamer , Mitch Gusat , Ronald P. Luijten , Cyriel Minkenberg , Mark Verhappen
发明人： Francois G. Abel , Wolfgang Denzel , Antonius Engbersen , Ferdinand Gramsamer , Mitch Gusat , Ronald P. Luijten , Cyriel Minkenberg , Mark Verhappen
IPC分类号： H04L12/56
CPC分类号： H04L47/6215 , H04L47/10 , H04L47/2433 , H04L47/2458 , H04L47/30 , H04L49/90
摘要： The present invention discloses a memory sharing mechanism based on priority elevation. In accordance with the present invention, there is provided an apparatus and method for transporting packets of data in a communication device, wherein each packet is assigned one of several priorities and received based on memory state information. The method comprises the steps of storing the received packets in a memory and modifying the assigned priority of any of the packets causing congestion within the memory.
摘要翻译：本发明公开了一种基于优先级提升的存储器共享机制。根据本发明，提供了一种用于在通信设备中传送数据分组的装置和方法，其中每个分组被分配为几个优先级中的一个并且基于存储器状态信息来接收。该方法包括以下步骤：将接收到的分组存储在存储器中，并修改任何分组的分配优先级，从而导致存储器内的拥塞。

17. 发明授权

US07197540B2 Control logic implementation for a non-blocking switch network 失效
标题翻译：非阻塞交换机网络的控制逻辑实现
公开(公告)号：US07197540B2
公开(公告)日：2007-03-27
申请号：US10093920
申请日：2002-03-08
申请人： Gottfried A. Goldrian , Bernd Leppla , Norbert Schumacher , Francois Abel , Ronald P. Luijten
发明人： Gottfried A. Goldrian , Bernd Leppla , Norbert Schumacher , Francois Abel , Ronald P. Luijten
IPC分类号： G06F15/167
CPC分类号： G06F15/17393 , H04L49/101 , H04L49/1546 , H04L49/25 , H04L49/3018 , H04L49/3027
摘要： The present invention relates to switching technology in computer networks and in particular to a method and system for switching information packets through a m input, n output device. According to the invention it is proposed to temporarily buffer said packets according to a new, self-explanatory, preferred a linear addressing scheme in which a respective buffer location of consecutive stream packets results from a respective self-explanatory, or linear, respectively, incrementation of a buffer pointer. Preferably, a matrix of FIFO storage elements (10,11,12,13) having an input and an output crossbar can be used for implementing input/output paralleling modes (ILP,OLP) and multiple lanes and achieving address input/output scaling up to a single cycle.
摘要翻译：本发明涉及计算机网络中的切换技术，特别涉及一种通过m输入输出设备切换信息分组的方法和系统。根据本发明，提出根据一种新的，不言自明的优选的线性寻址方案临时缓冲所述分组，其中连续流分组的相应缓冲器位置分别由相应的不说明的或线性的递增的缓冲区指针。优选地，可以使用具有输入和输出交叉开关的FIFO存储元件（10,11,12,13）的矩阵来实现输入/输出并行模式（ILP，OLP）和多个通道，并且实现地址输入/输出放大到一个周期。

18. 发明授权

US06996116B2 Switching nodes and interface modules for data networks 有权
标题翻译：用于数据网络的交换节点和接口模块
公开(公告)号：US06996116B2
公开(公告)日：2006-02-07
申请号：US09991295
申请日：2001-11-21
申请人： Ton Engbersen , Ronald P. Luijten
发明人： Ton Engbersen , Ronald P. Luijten
IPC分类号： H04L12/56
CPC分类号： H04L49/25 , H04L49/10 , H04L49/30 , H04L49/351
摘要： An interface module is provided for connecting a data communications link to a switching node, comprising a plurality of other interface modules, of a data communications network. The interface module has at least one external port for connection to a data communications link, and a plurality of internal ports for connection to respective internal ports of the switching node. A link interface is connected to the external port for processing inbound and outbound data. A switch circuit is connected between the link interface and the internal ports of the module for transmission of data between the internal ports and to the link interface. The module includes a controller for controlling routing of data via the internal ports in accordance with an intra-node routing protocol. Switching nodes comprising a plurality of interface modules, and optionally one or more switching modules, are provided.
摘要翻译：提供了一种用于将数据通信链路连接到包括数据通信网络的多个其他接口模块的交换节点的接口模块。接口模块具有用于连接到数据通信链路的至少一个外部端口和用于连接到交换节点的相应内部端口的多个内部端口。链路接口连接到外部端口，用于处理入站和出站数据。链路接口和模块的内部端口之间连接有一个开关电路，用于在内部端口和链路接口之间传输数据。该模块包括控制器，用于根据节点间路由协议控制经由内部端口的数据路由。提供包括多个接口模块和可选地一个或多个交换模块的交换节点。

19. 发明授权

US6044077A Method and apparatus for ATM switching 失效
标题翻译： ATM交换的方法和装置
公开(公告)号：US6044077A
公开(公告)日：2000-03-28
申请号：US860772
申请日：1997-07-07
申请人： Ronald P. Luijten , David J. Webb
发明人： Ronald P. Luijten , David J. Webb
IPC分类号： H04Q3/00 , H04L12/28 , H04L12/935 , H04Q11/04 , H04L12/56
CPC分类号： H04L49/3081 , H04Q11/0478
摘要： A switch for use in an ATM network is disclosed. The switch is designed to perform a function beyond that normally achievable with a virtual path switch functioning in accordance with the ATM standard. The switch according to the invention has data stored in a look-up table (431-433) which allows it to identify communication cells of particular individual virtual channels, indicated by the virtual path identifier (VCI), although these cells cannot be distinguished on the basis of their virtual path indicators (VPIs). This identification is attempted before the usual step of forwarding an incoming communication cell based solely on its virtual path indicator. A priority circuitry (44) ensures that entries associated with the combined VPI/VCI is given a priority over those associated only with the VPI. The switch can extract cells of individual virtual channels passing through it. It can also insert virtual channels into the ATM network.
摘要翻译： PCT No.PCT / EP95 / 00276 Sec。 371日期1997年7月7日 102（e）日期1997年7月7日PCT 1995年1月26日PCT PCT。公开号WO96 / 23391 日期：1996年8月1日公开了一种在ATM网络中使用的开关。该交换机被设计为执行超出通常根据ATM标准工作的虚拟路径交换机可实现的功能。根据本发明的交换机具有存储在查找表（431-433）中的数据，其允许其识别由虚拟路径标识符（VCI）指示的特定单个虚拟信道的通信小区，尽管这些小区不能在其虚拟路径指标（VPI）的基础。在基于其虚拟路径指示符转发传入通信小区的通常步骤之前尝试该标识。优先级电路（44）确保与组合的VPI / VCI相关联的条目被优先于仅与VPI相关联的条目。交换机可以提取通过它的各个虚拟通道的单元。它还可以将虚拟通道插入ATM网络。

20. 发明授权

US08930716B2 Address translation unit, device and method for remote direct memory access of a memory 有权
标题翻译：用于存储器的远程直接存储器访问的地址转换单元，设备和方法
公开(公告)号：US08930716B2
公开(公告)日：2015-01-06
申请号：US13617942
申请日：2012-09-14
申请人： Florian A. Auernhammer , Nikolaos Chrysos , Rolf Clauberg , Andreas C. Doering , Ronald P. Luijten , Patricia M. Sagmeister
发明人： Florian A. Auernhammer , Nikolaos Chrysos , Rolf Clauberg , Andreas C. Doering , Ronald P. Luijten , Patricia M. Sagmeister
IPC分类号： G06F11/30 , G06F12/10 , H04L9/00 , H04L9/08 , H04L9/32 , G06F12/14
CPC分类号： G06F12/1081 , G06F12/1408 , H04L9/00 , H04L9/0894 , H04L9/3247 , Y02D10/13
摘要： A method for Remote Direct Memory Access (RDMA) of a memory of a processor. An address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address.
摘要翻译：一种用于处理器存储器的远程直接存储器访问（RDMA）的方法。地址转换单元包括地址转换器和签名者。地址转换器被配置为在存储器的实际地址中转换接收的虚拟地址。签名者被配置为对真实地址进行加密签名。

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