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11. 发明授权

US09025393B2 Method of optimizing solid state drive soft retry voltages 有权
标题翻译：优化固态硬盘软重试电压的方法
公开(公告)号：US09025393B2
公开(公告)日：2015-05-05
申请号：US13856179
申请日：2013-04-03
申请人： LSI Corporation
发明人： Yunxiang Wu , Zhengang Chen , YingQuan Wu , Ning Chen
IPC分类号： G11C11/56 , G11C29/42 , G11C16/00 , G11C29/02 , G11C29/50
CPC分类号： G11C11/5642 , G11C16/00 , G11C29/023 , G11C29/028 , G11C29/42 , G11C29/50004
摘要： A method of optimizing solid state drive (SSD) soft retry voltages comprises limiting a number of voltage reads and properly spacing and determining the reference voltage at which each voltage is read based on desired Bit Error Rate (BER) and channel throughput. The method determines each reference voltage for a number of soft retry voltage reads based on a hard decision read. The spacing between each read reference voltage is constant since each SSD type requires a number of reads for an accurate presentation of soft retry voltages. The voltage distance between each successive read is limited to a multiple of the constant spacing while the multiple is based on success or failure of the first read. The method determines a limited number of reads, the constant spacing between reads, and a desired reference voltage for each read, thereby increasing valuable throughput of the channel and decreasing BER.
摘要翻译：优化固态驱动（SSD）软重试电压的方法包括基于所需的误码率（BER）和信道吞吐量来限制多个电压读取和适当的间隔并确定读取每个电压的参考电压。该方法基于硬判决读取确定多个软重试电压读取的每个参考电压。每个读取参考电压之间的间距是恒定的，因为每个SSD类型需要多个读取以精确呈现软重试电压。每个连续读取之间的电压距离被限制为恒定间隔的倍数，而倍数是基于第一次读取的成功或失败。该方法确定读数的有限数量，读取之间的恒定间隔和每次读取的期望参考电压，从而增加了信道的有价值的吞吐量并降低了BER。

12. 发明申请

US20150092489A1 FLASH MEMORY REFERENCE VOLTAGE DETECTION WITH TRACKING OF CROSS-POINTS OF CELL VOLTAGE DISTRIBUTIONS USING HISTOGRAMS 有权
标题翻译：使用组织图跟踪电池电压分布的点的闪存参考电压检测
公开(公告)号：US20150092489A1
公开(公告)日：2015-04-02
申请号：US14059229
申请日：2013-10-21
申请人： LSI Corporation
发明人： Yunxiang Wu , Abdel-Hakim Alhussien , Zhengang Chen , Sundararajan Sankaranarayanan , Erich F. Haratsch
IPC分类号： G11C16/10
CPC分类号： G11C16/26 , G11C7/14 , G11C11/5642 , G11C16/349 , G11C29/021 , G11C29/028
摘要： Cross-points of flash memory cell voltage distributions are determined by reading data from a portion of the flash memory two or more times using two or more different candidate reference voltages and determining corresponding decision patterns. The frequency of occurrence of the decision patterns in the data read from the flash memory is used to conceptually construct a histogram. The histogram is used to estimate the cross-points. Employing decision patterns enables multiple cross-point voltages to be determined with a minimum of read operations.
摘要翻译：通过使用两个或更多个不同的候选参考电压从闪速存储器的一部分读取数据两次或更多次来确定快闪存储器单元电压分布的交点，并确定相应的判定模式。使用从闪存读取的数据中的判定模式的发生频率来概念地构造直方图。直方图用于估计交叉点。采用决策模式可以通过最少的读取操作来确定多个交叉点电压。

13. 发明申请

US20140286102A1 Method of Optimizing Solid State Drive Soft Retry Voltages 有权
标题翻译：优化固态硬盘软重试电压的方法
公开(公告)号：US20140286102A1
公开(公告)日：2014-09-25
申请号：US13856179
申请日：2013-04-03
申请人： LSI CORPORATION
发明人： Yunxiang Wu , Zhengang Chen , YingQuan Wu , Ning Chen
IPC分类号： G11C29/04
CPC分类号： G11C11/5642 , G11C16/00 , G11C29/023 , G11C29/028 , G11C29/42 , G11C29/50004
摘要： A method of optimizing solid state drive (SSD) soft retry voltages comprises limiting a number of voltage reads and properly spacing and determining the reference voltage at which each voltage is read based on desired Bit Error Rate (BER) and channel throughput. The method determines each reference voltage for a number of soft retry voltage reads based on a hard decision read. The spacing between each read reference voltage is constant since each SSD type requires a number of reads for an accurate presentation of soft retry voltages. The voltage distance between each successive read is limited to a multiple of the constant spacing while the multiple is based on success or failure of the first read. The method determines a limited number of reads, the constant spacing between reads, and a desired reference voltage for each read, thereby increasing valuable throughput of the channel and decreasing BER.
摘要翻译：优化固态驱动（SSD）软重试电压的方法包括基于所需的误码率（BER）和信道吞吐量来限制多个电压读取和适当的间隔并确定读取每个电压的参考电压。该方法基于硬判决读取确定多个软重试电压读取的每个参考电压。每个读取参考电压之间的间距是恒定的，因为每个SSD类型需要多个读取以精确呈现软重试电压。每个连续读取之间的电压距离被限制为恒定间隔的倍数，而倍数是基于第一次读取的成功或失败。该方法确定读数的有限数量，读取之间的恒定间隔和每次读取的期望参考电压，从而增加了信道的有价值的吞吐量并降低了BER。

14. 发明申请

US20140164880A1 ERROR CORRECTION CODE RATE MANAGEMENT FOR NONVOLATILE MEMORY 有权
标题翻译：非易失性存储器的错误校正代码率管理
公开(公告)号：US20140164880A1
公开(公告)日：2014-06-12
申请号：US13798696
申请日：2013-03-13
申请人： LSI CORPORATION
发明人： Zhengang Chen , Jeremy Werner , Earl T. Cohen , Ning Chen , AbdelHakim S. Alhussien , Erich F. Haratsch
IPC分类号： G06F11/10
CPC分类号： G06F11/1012
摘要： An apparatus having an interface and a circuit is shown. The interface is coupled to a memory that is nonvolatile. The circuit is configured to (i) read a plurality of codewords from a block in the memory based on a program/erase count associated with the block, (ii) count a number of iterations used to decode the codewords and (iii) decrease a code rate of an error correction coding used to program the block in response to the number of iterations exceeding a threshold.
摘要翻译：示出了具有接口和电路的装置。该接口耦合到非易失性存储器。电路被配置为（i）基于与该块相关联的编程/擦除计数，从存储器中的块读取多个码字，（ii）对用于解码码字的迭代次数进行计数，以及（iii）减少一个用于响应于超过阈值的迭代次数来编程块的纠错编码的码率。

15. 发明申请

US20150294739A1 ONLINE HISTOGRAM AND SOFT INFORMATION LEARNING 审中-公开
标题翻译：在线学习和软件信息学习
公开(公告)号：US20150294739A1
公开(公告)日：2015-10-15
申请号：US14249714
申请日：2014-04-10
申请人： LSI Corporation
发明人： Yu Cai , Zhengang Chen , Yunxiang Wu , Erich F. Haratsch
IPC分类号： G11C29/50 , G06F11/10 , G06F11/07 , G11C29/44
CPC分类号： G11C16/349 , G06F11/1012 , G11C11/5642 , G11C29/021 , G11C29/028 , G11C29/42 , G11C2029/0411
摘要： A system includes a processor configured to read information from a plurality of memory cells. The processor initiates a first read of raw data from a group of memory cells using a first reference voltage. The processor also initiates a second read of raw data from the group of memory cells using a second reference voltage different from the first reference voltage. The processor further compares the first read to the second read to identify memory cells read with a bit value that changes between the first and second reads. The processor also assigns the memory cells read with a bit value that changes between the first and second reads to a region associated with the second reference voltage. The processor further counts the number of cells read with a bit value that changes to generate a histogram corresponding to soft information for the group of memory cells.
摘要翻译：系统包括被配置为从多个存储单元读取信息的处理器。处理器使用第一参考电压启动来自一组存储器单元的原始数据的第一次读取。处理器还使用不同于第一参考电压的第二参考电压来启动来自存储器单元组的原始数据的第二次读取。处理器进一步将第一次读取与第二次读取进行比较，以识别用第一次读取和第二次读取之间改变的位值读取的存储器单元。处理器还将读取的存储器单元分配为在第一和第二读取之间变化到与第二参考电压相关联的区域的位值。处理器进一步用改变的位值对读取的单元的数量进行计数，以产生对应于该组存储器单元的软信息的直方图。

16. 发明申请

US20150227314A1 Systems and Methods for Last Written Page Handling in a Memory Device 有权
标题翻译：存储设备中最后写入页面处理的系统和方法
公开(公告)号：US20150227314A1
公开(公告)日：2015-08-13
申请号：US14192831
申请日：2014-02-27
申请人： LSI Corporation
发明人： Zhengang Chen , Yu Cai , Erich F. Haratsch , Zhimin Dong
IPC分类号： G06F3/06 , G06F11/10
CPC分类号： G06F11/1068 , G06F11/1012 , G11C11/5642 , G11C16/28 , G11C29/52 , G11C2211/5634 , G11C2211/5641 , H03M13/37
摘要： Systems and method relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory.
摘要翻译：一般涉及固态存储器的系统和方法，更具体地涉及用于从固态存储器恢复数据的系统和方法。

17. 发明授权

US09053804B2 Reduced complexity reliability computations for flash memories 有权
标题翻译：降低闪存的复杂度可靠性计算
公开(公告)号：US09053804B2
公开(公告)日：2015-06-09
申请号：US13777484
申请日：2013-02-26
申请人： LSI Corporation
发明人： Yunxiang Wu , Zhengang Chen
IPC分类号： G11C16/26 , G11C11/56
CPC分类号： G11C16/26 , G11C11/5642
摘要： Methods and apparatus are provided for computing reliability values, such as log likelihood ratios (LLRs), with reduced complexity for flash memory devices. Data from a flash memory device that stores M bits per cell using 2^M possible states is processed by obtaining at least two soft read voltage values corresponding to two reference voltages V0 and V1, wherein the two reference voltages V0 and V1 are between two adjacent states of the 2^M possible states; and converting the at least two soft read voltage values to a log likelihood ratio for a region between the two reference voltages V0 and V1 using probability density functions only for the two adjacent states. The soft read voltage values comprise, for example, hard decision read values obtained by a plurality of read retries of a given cell at a plurality of reference voltages and/or soft values obtained from the flash memory device.
摘要翻译：提供了用于计算可靠性值（例如对数似然比（LLR））的方法和装置，其具有降低的闪存器件的复杂性。通过获得对应于两个参考电压V0和V1的至少两个软读取电压值来处理来自使用2 ^ M个可能状态存储每个单元的M位的闪存器件的数据，其中两个参考电压V0和V1在两个相邻 2个可能状态的状态; 以及仅使用两个相邻状态的概率密度函数将所述至少两个软读取电压值转换为两个参考电压V0和V1之间的区域的对数似然比。软读取电压值包括例如通过从闪速存储器件获得的多个参考电压和/或软值的给定单元的多次读取重试获得的硬判定读取值。

18. 发明授权

US09021332B2 Flash memory read error recovery with soft-decision decode 有权
标题翻译：闪存读取错误恢复与软判决解码
公开(公告)号：US09021332B2
公开(公告)日：2015-04-28
申请号：US13798864
申请日：2013-03-13
申请人： LSI Corporation
发明人： Erich F. Haratsch , Jeremy Werner , Zhengang Chen , Earl T. Cohen , Yunxiang Wu , Ning Chen
IPC分类号： G11C29/00 , G06F11/10 , H03M13/37 , H03M13/00 , H03M13/11 , H03M13/39 , H03M13/41
CPC分类号： G06F11/1068 , G06F11/1012 , G11C29/52 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/3707 , H03M13/3905 , H03M13/41 , H03M13/45 , H03M13/6561
摘要： An apparatus having a circuit and one or more processor is disclosed. The circuit is configured to receive a codeword from a memory. The memory is nonvolatile. The codeword generally has one or more errors. The processors are configured to generate read data by decoding the codeword repeatedly. The decoding includes a soft-decision decoding that uses a plurality of parameters calculated by (i) a first procedure, (ii) a second procedure in response to a plurality of failures of the decoding to converge using the first procedure and (iii) a third procedure in response to another failure of the decoding to converge using the second procedure.
摘要翻译：公开了一种具有电路和一个或多个处理器的装置。电路被配置为从存储器接收码字。存储器是非易失性的。码字通常具有一个或多个错误。处理器被配置为通过重复地解码码字来生成读取数据。解码包括软判决解码，其使用通过（i）第一过程计算的多个参数，（ii）响应于解码的多个故障使用第一过程收敛的第二过程，以及（iii）响应于使用第二过程的解码收敛的另一个故障的第三过程。

19. 发明授权

US08854880B2 Inter-cell interference cancellation in flash memories 有权
标题翻译：闪存中的单元间干扰消除
公开(公告)号：US08854880B2
公开(公告)日：2014-10-07
申请号：US13778860
申请日：2013-02-27
申请人： LSI Corporation
发明人： Zhengang Chen , Erich F. Haratsch
IPC分类号： G11C11/34 , G11C11/56 , G11C16/04
CPC分类号： G11C16/04 , G11C11/5642
摘要： Inter-cell interference cancellation is provided for flash memory devices. Data from a flash memory device is processed by obtaining one or more quantized threshold voltage values for at least one target cell of the flash memory device; obtaining one or more hard decision read values for at least one aggressor cell of the target cell; determining an aggressor state of the at least one aggressor cell; determining an interference amount based on the aggressor state; determining an adjustment to the quantized threshold voltage values based on the determined interference amount; and adjusting the quantized threshold voltage values based on the determined adjustment. The quantized threshold voltage values for at least one target cell are optionally re-used from a previous soft read retry operation. The adjusted quantized threshold voltage values are optionally used to determine reliability values and are optionally applied to a soft decision decoder and/or a buffer.
摘要翻译：为闪存设备提供了小区间干扰消除。通过为闪存器件的至少一个目标单元获得一个或多个量化的阈值电压值来处理闪存器件的数据; 获得目标小区的至少一个攻击者小区的一个或多个硬判决读取值; 确定所述至少一个侵略者小区的侵略者状态; 基于侵略者状态确定干扰量; 基于所确定的干扰量确定对所述量化阈值电压值的调整; 以及基于所确定的调整来调整所述量化阈值电压值。可选地，从先前的软读取重试操作重新使用至少一个目标单元的量化阈值电压值。调整的量化阈值电压值可选地用于确定可靠性值，并且可选地应用于软判决解码器和/或缓冲器。

20. 发明申请

US20140164868A1 FLASH MEMORY READ ERROR RECOVERY WITH SOFT-DECISION DECODE 有权
标题翻译： FLASH MEMORY读取错误恢复与软决策解码
公开(公告)号：US20140164868A1
公开(公告)日：2014-06-12
申请号：US13798864
申请日：2013-03-13
申请人： LSI CORPORATION
发明人： Erich F. Haratsch , Jeremy Werner , Zhengang Chen , Earl T. Cohen , Yunxiang Wu , Ning Chen
IPC分类号： G06F11/10
CPC分类号： G06F11/1068 , G06F11/1012 , G11C29/52 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/3707 , H03M13/3905 , H03M13/41 , H03M13/45 , H03M13/6561
摘要： An apparatus having a circuit and one or more processor is disclosed. The circuit is configured to receive a codeword from a memory. The memory is nonvolatile. The codeword generally has one or more errors. The processors are configured to generate read data by decoding the codeword repeatedly. The decoding includes a soft-decision decoding that uses a plurality of parameters calculated by (i) a first procedure, (ii) a second procedure in response to a plurality of failures of the decoding to converge using the first procedure and (iii) a third procedure in response to another failure of the decoding to converge using the second procedure.
摘要翻译：公开了一种具有电路和一个或多个处理器的装置。电路被配置为从存储器接收码字。存储器是非易失性的。码字通常具有一个或多个错误。处理器被配置为通过重复地解码码字来生成读取数据。解码包括软判决解码，其使用通过（i）第一过程计算的多个参数，（ii）响应于解码的多个故障使用第一过程收敛的第二过程，以及（iii）响应于使用第二过程的解码收敛的另一个故障的第三过程。

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