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11. 发明申请

US20050282363A1 Method of forming fine pattern of semiconductor device using SiGe layer as sacrificial layer, and method of forming self-aligned contacts using the same 有权
标题翻译：使用SiGe层作为牺牲层形成精细图案的半导体器件的方法以及使用其形成自对准触点的方法
公开(公告)号：US20050282363A1
公开(公告)日：2005-12-22
申请号：US11157435
申请日：2005-06-21
申请人： Keun-Hee Bai , Kyeong-Koo Chi , Chang-Jin Kang , Cheol-Kyu Lee
发明人： Keun-Hee Bai , Kyeong-Koo Chi , Chang-Jin Kang , Cheol-Kyu Lee
IPC分类号： H01L21/027 , H01L21/033 , H01L21/36 , H01L21/469 , H01L21/60
CPC分类号： H01L21/0331 , H01L21/0332 , H01L21/76897
摘要： There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si1-xGex) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched. Then, the region where the sacrificial layer is removed is filled with silicon oxide, thereby forming a first interlayer insulating layer.
摘要翻译：提供了使用硅锗牺牲层形成半导体器件的精细图案的方法，以及使用其形成自对准接触的方法。形成半导体器件的自对准接触的方法包括在衬底上形成具有导电材料层，硬掩模层和侧壁间隔物的导电线结构，并且形成硅锗（Si 1-Si） xTi）x牺牲层，其具有等于或高于至少导电线结构的高度的高度，在基底的整个表面上。然后，在牺牲层上形成用于限定接触孔的光致抗蚀剂图案，并且牺牲层被干蚀刻，从而形成用于使基板曝光的接触孔。使用多晶硅形成用于填充接触孔的多个触点，并且将残留的牺牲层湿式蚀刻。然后，用氧化硅填充除去牺牲层的区域，从而形成第一层间绝缘层。

12. 发明授权

US07879726B2 Methods of forming semiconductor devices using selective etching of an active region through a hardmask 有权
标题翻译：通过硬掩模选择性蚀刻活性区域形成半导体器件的方法
公开(公告)号：US07879726B2
公开(公告)日：2011-02-01
申请号：US12187895
申请日：2008-08-07
申请人： Heung-Sik Park , Jun-Ho Yoon , Cheol-Kyu Lee , Joon-Soo Park
发明人： Heung-Sik Park , Jun-Ho Yoon , Cheol-Kyu Lee , Joon-Soo Park
IPC分类号： H01L21/311
CPC分类号： H01L21/3081 , H01L21/3065 , H01L29/4236 , H01L29/66621
摘要： A method of fabricating a semiconductor device is provided. The method can include forming a hard mask film including lower and upper hard mask films on a substrate in which an active region and an isolation region are defined and patterning the hard mask film to provide a hard mask pattern partially exposing the active region and the isolation region. An etchant can be applied to the active and isolation regions using the hard mask pattern as an etching mask to form a trench in the active region of the substrate while avoiding substantially etching the isolation region exposed to the etchant and a gate can be formed on the trench.
摘要翻译：提供一种制造半导体器件的方法。该方法可以包括在其上限定有源区和隔离区的衬底上形成包括下硬掩模膜和上硬掩模膜的硬掩模膜，并对硬掩模膜进行构图以提供部分暴露有源区的硬掩模图案和隔离地区。可以使用硬掩模图案作为蚀刻掩模将蚀刻剂施加到有源和隔离区域，以在衬底的有源区域中形成沟槽，同时避免基本上蚀刻暴露于蚀刻剂的隔离区域，并且可以在栅极上形成栅极沟。

13. 发明授权

US07763544B2 Method of forming fine pattern of semiconductor device using sige layer as sacrificial layer, and method of forming self-aligned contacts using the same 有权
标题翻译：使用精密层作为牺牲层形成精细图案的方法，以及使用其形成自对准触点的方法
公开(公告)号：US07763544B2
公开(公告)日：2010-07-27
申请号：US12496108
申请日：2009-07-01
申请人： Keun-Hee Bai , Kyeong-Koo Chi , Chang-Jin Kang , Cheol-Kyu Lee
发明人： Keun-Hee Bai , Kyeong-Koo Chi , Chang-Jin Kang , Cheol-Kyu Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/0331 , H01L21/0332 , H01L21/76897
摘要： There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si1-xGex) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched. Then, the region where the sacrificial layer is removed is filled with silicon oxide, thereby forming a first interlayer insulating layer.
摘要翻译：提供了使用硅锗牺牲层形成半导体器件的精细图案的方法，以及使用其形成自对准接触的方法。形成半导体器件的自对准接触的方法包括在衬底上形成具有导电材料层，硬掩模层和侧壁间隔物的导电线结构，以及形成硅锗（Si1-xGex）牺牲层，其具有等于或高于至少导电线结构的高度的高度，在基板的整个表面上。然后，在牺牲层上形成用于限定接触孔的光致抗蚀剂图案，并且牺牲层被干蚀刻，从而形成用于使基板曝光的接触孔。使用多晶硅形成用于填充接触孔的多个触点，并且将残留的牺牲层湿式蚀刻。然后，用氧化硅填充除去牺牲层的区域，从而形成第一层间绝缘层。

14. 发明授权

US07566659B2 Method of forming fine pattern of semiconductor device using SiGe layer as sacrificial layer, and method of forming self-aligned contacts using the same 有权
标题翻译：使用SiGe层作为牺牲层形成精细图案的半导体器件的方法以及使用其形成自对准触点的方法
公开(公告)号：US07566659B2
公开(公告)日：2009-07-28
申请号：US11157435
申请日：2005-06-21
申请人： Keun-Hee Bai , Kyeong-Koo Chi , Chang-Jin Kang , Cheol-Kyu Lee
发明人： Keun-Hee Bai , Kyeong-Koo Chi , Chang-Jin Kang , Cheol-Kyu Lee
IPC分类号： H01L21/44
CPC分类号： H01L21/0331 , H01L21/0332 , H01L21/76897
摘要： There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si1-xGex) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched. Then, the region where the sacrificial layer is removed is filled with silicon oxide, thereby forming a first interlayer insulating layer.
摘要翻译：提供了使用硅锗牺牲层形成半导体器件的精细图案的方法，以及使用其形成自对准接触的方法。形成半导体器件的自对准接触的方法包括在衬底上形成具有导电材料层，硬掩模层和侧壁间隔物的导电线结构，以及形成硅锗（Si1-xGex）牺牲层，其具有等于或高于至少导电线结构的高度的高度，在基板的整个表面上。然后，在牺牲层上形成用于限定接触孔的光致抗蚀剂图案，并且牺牲层被干蚀刻，从而形成用于使基板曝光的接触孔。使用多晶硅形成用于填充接触孔的多个触点，并且将残留的牺牲层湿式蚀刻。然后，用氧化硅填充除去牺牲层的区域，从而形成第一层间绝缘层。

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