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11. 发明申请

US20120001680A1 ISOLATION CIRCUIT 有权
标题翻译：隔离电路
公开(公告)号：US20120001680A1
公开(公告)日：2012-01-05
申请号：US13211022
申请日：2011-08-16
申请人： Hani S. Attalla , Daniel P. Cram
发明人： Hani S. Attalla , Daniel P. Cram
IPC分类号： H03K3/01
CPC分类号： G01R31/2884 , G01R31/31721 , G01R31/31723 , H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure includes various method, device, and system embodiments for isolation circuits. One such isolation circuit embodiment includes: a first transistor configured for connection to a supply voltage via a first terminal; a register connected to the first transistor; a second transistor in parallel with a resistor, wherein the second transistor is configured for connection to the first terminal, with a gate of the second transistor configured for connection to an output of the register; and wherein the second transistor is configured for connection to a second terminal, the second transistor having a state that depends on a status of the register.
摘要翻译：本公开包括用于隔离电路的各种方法，装置和系统实施例。一个这样的隔离电路实施例包括：第一晶体管，被配置为经由第一端子连接到电源电压; 连接到第一晶体管的寄存器; 与电阻器并联的第二晶体管，其中所述第二晶体管被配置为连接到所述第一端子，所述第二晶体管的栅极被配置为连接到所述寄存器的输出; 并且其中所述第二晶体管被配置为连接到第二端子，所述第二晶体管具有取决于所述寄存器的状态的状态。

12. 发明授权

US08063646B2 Apparatus and methods for testing microelectronic devices 有权
标题翻译：用于测试微电子器件的装置和方法
公开(公告)号：US08063646B2
公开(公告)日：2011-11-22
申请号：US11509292
申请日：2006-08-23
申请人： Daniel P. Cram , A. Jay Stutzman
发明人： Daniel P. Cram , A. Jay Stutzman
IPC分类号： G01R31/02
CPC分类号： G01R31/286
摘要： Microelectronic devices, methods for testing microelectronic devices, and detachable electrical components. One embodiment of an apparatus for testing microelectronic devices in accordance with the invention comprises a board having a primary side, a secondary side, a plurality of test sites at the primary side, and electrical lines electrically coupled to the test sites. The testing apparatus can further include a plurality of lead holes in the board. Individual lead holes have a sidewall and a conductive section plated onto the sidewall. In several embodiments, individual pairs of first and second lead holes are electrically coupled to electrical lines corresponding to an associated test site. The apparatus can further include a plurality of permanent fuses fixed to the board. Individual permanent fuses are electrically coupled to electrical lines associated with an individual test site and an individual pair of first and second lead holes. The testing apparatus can further include a replacement fuse mounted to an individual pair of first and second lead holes at a test site having a blown permanent fuse. The replacement fuse has a first lead with a press-fit member engaged directly with the plated section in the first lead hole. The replacement fuse further includes a second lead engaged with the second lead hole and a fuse element connected in series with the first and second leads.
摘要翻译：微电子器件，微电子器件的测试方法和可拆卸的电气部件。根据本发明的用于测试微电子器件的装置的一个实施例包括具有初级侧，次级侧，初级侧的多个测试位置和电耦合到测试位置的电线的板。测试装置还可以包括在板中的多个引线孔。单独的引线孔具有镀在侧壁上的侧壁和导电部分。在几个实施例中，单独的第一和第二引线对被电耦合到对应于相关测试位置的电线。该装置还可以包括多个固定在板上的永久保险丝。单独的永久保险丝电耦合到与单个测试位置和单独的一对第一和第二引线孔相关联的电线。测试装置还可以包括在具有熔断的永久熔断器的测试位置处安装到单独的一对第一和第二引线孔的替换保险丝。替换保险丝具有第一引线，其中压合构件直接与第一引线孔中的电镀部分接合。替换保险丝还包括与第二引线孔接合的第二引线和与第一引线和第二引线串联连接的熔丝元件。

13. 发明申请

US20090273359A1 ELECTRICAL TESTING APPARATUS HAVING MASKED SOCKETS AND ASSOCIATED SYSTEMS AND METHODS 失效
标题翻译：带屏蔽插座及相关系统及方法的电气测试装置
公开(公告)号：US20090273359A1
公开(公告)日：2009-11-05
申请号：US12114661
申请日：2008-05-02
申请人： A. Jay Stutzman , Daniel P. Cram
发明人： A. Jay Stutzman , Daniel P. Cram
IPC分类号： G01R1/04 , H01R13/60
CPC分类号： H01R13/2407 , G01R1/0466 , H01R12/716 , H01R2201/20
摘要： An apparatus for forming a temporary electrical connection with a microelectronic component and associated systems and methods are disclosed herein. Embodiments of the apparatus can include a base, a plurality of electrical contacts coupled to the base, and a nest attached to the base. The nest includes a plurality of contact compartments aligned with peripheral leads of the microelectronic component and at least partially covering the contacts. Individual contact compartments are masked to prevent a corresponding contact from electrically contacting the peripheral leads of the microelectronic component. In one embodiment, the masked contact compartments are used as a guide zone to guide individual peripheral leads when the microelectronic component is seated at or unseated from the support surface. In an additional or alternative embodiment, the masked contact compartments are used to selectively isolate contacts, for example, from supply or ground electrical potentials.
摘要翻译：本文公开了一种用于形成具有微电子部件的临时电连接的装置以及相关联的系统和方法。该装置的实施例可以包括底座，联接到基座的多个电触点和附接到基座的嵌套。巢包括与微电子部件的外围引线对准并且至少部分地覆盖触点的多个接触隔室。单独的接触隔室被掩蔽以防止相应的接触件电接触微电子部件的外围引线。在一个实施例中，当微电子部件位于支撑表面或从支撑表面移开时，被掩蔽的接触隔室用作引导区域以引导各个外围引线。在附加或替代实施例中，掩蔽的接触隔室用于选择性地隔离触点，例如与电源或接地电位。

14. 发明授权

US07586319B2 Methods of retaining semiconductor component configurations within sockets 失效
标题翻译：在插座内保持半导体部件配置的方法
公开(公告)号：US07586319B2
公开(公告)日：2009-09-08
申请号：US12208456
申请日：2008-09-11
申请人： Daniel P. Cram , A. Jay Stutzman
发明人： Daniel P. Cram , A. Jay Stutzman
IPC分类号： G01R31/02
CPC分类号： G01R31/2891 , Y10T29/49128 , Y10T29/4913 , Y10T29/49131 , Y10T29/49133 , Y10T29/49169 , Y10T29/49174 , Y10T29/49204 , Y10T29/49208
摘要： The invention includes methods of utilizing removable mechanical precising mechanisms and/or optical-based precising mechanisms to align chips within sockets. The sockets can be configured so that compression of the sockets opens a clamping mechanism. A chip can be placed within a socket with a manipulator and aligned during compression of the socket. Subsequently, the compression of the socket can be released while the manipulator remains in contact with the chip to hold the chip in place until the clamping mechanism is retaining the chip in the socket. The chip can then be released from the manipulator. The invention also includes systems for utilizing removable nests to align various chip geometries within generic socket designs.
摘要翻译：本发明包括利用可拆卸的机械预处理机构和/或基于光学的精确机构来使芯片在插座内对准的方法。插座可以被配置为使得插座的压缩打开夹紧机构。芯片可以放置在具有操纵器的插座内，并在插座压缩期间对齐。随后，可以释放插座的压缩，同时操纵器保持与芯片接触以将芯片保持就位，直到夹持机构将芯片保持在插座中。然后可以从操纵器释放芯片。本发明还包括用于利用可拆卸嵌套将通用插座设计中的各种芯片几何形状对准的系统。

15. 发明授权

US07456504B2 Electronic component assemblies with electrically conductive bonds 有权
标题翻译：具有导电键的电子部件组件
公开(公告)号：US07456504B2
公开(公告)日：2008-11-25
申请号：US11599194
申请日：2006-11-13
申请人： Steven L. Hamren , Daniel P. Cram
发明人： Steven L. Hamren , Daniel P. Cram
IPC分类号： H01L29/40 , H01L23/48
CPC分类号： G01R1/0408 , G01R1/0433 , H01L24/13 , H01L24/16 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/00013 , H01L2924/00014 , H01L2924/01079 , H01L2924/01087 , H01L2924/09701 , H01L2924/14 , H01L2924/16195 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H05K3/321 , H01L2224/29099 , H01L2224/05599
摘要： Improved methods and apparatus are provided for the handling and testing of semiconductor devices. One embodiment comprises a die carrier for one or more semiconductor dice having very fine pitch electrical I/O (input/output) elements. The semiconductor dice are temporarily attached to the die carrier in singulated form to enable testing the dice with conventional contact technology. The die carrier may include a flex circuit base substrate and a rigid support frame. Further embodiments comprise materials and methods for attaching the semiconductor dice to the die carrier and for providing a temporary electrical connection with the semiconductor dice during testing. Exemplary materials for providing the temporary electrical connection may comprise a conductive film or tape, a conductive or conductor-filled epoxy, resin or RTV adhesive-based materials, a water-soluble material impregnated with a conductive filler or non-reflowed solder paste.
摘要翻译：为半导体器件的处理和测试提供了改进的方法和设备。一个实施例包括用于一个或多个具有非常细间距的电I / O（输入/输出）元件的半导体管芯的管芯载体。半导体裸片以单一形式临时附接到模具载体，以便能够用常规接触技术测试骰子。模具载体可以包括柔性电路基底基板和刚性支撑框架。另外的实施例包括用于将半导体管芯附接到管芯载体并用于在测试期间提供与半导体管芯的临时电连接的材料和方法。用于提供临时电连接的示例性材料可以包括导电膜或带，导电或导体填充的环氧树脂或基于RTV粘合剂的材料，浸渍有导电填料或非回流焊膏的水溶性材料。

16. 发明授权

US07439752B2 Methods of providing semiconductor components within sockets 有权
标题翻译：在插座内提供半导体元件的方法
公开(公告)号：US07439752B2
公开(公告)日：2008-10-21
申请号：US11418724
申请日：2006-05-03
申请人： Daniel P. Cram , A. Jay Stutzman
发明人： Daniel P. Cram , A. Jay Stutzman
IPC分类号： G01R31/02
CPC分类号： G01R31/2891 , Y10T29/49128 , Y10T29/4913 , Y10T29/49131 , Y10T29/49133 , Y10T29/49169 , Y10T29/49174 , Y10T29/49204 , Y10T29/49208
摘要： The invention includes methods of utilizing removable mechanical precising mechanisms and/or optical-based precising mechanisms to align chips within sockets. The sockets can be configured so that compression of the sockets opens a clamping mechanism. A chip can be placed within a socket with a manipulator and aligned during compression of the socket. Subsequently, the compression of the socket can be released while the manipulator remains in contact with the chip to hold the chip in place until the clamping mechanism is retaining the chip in the socket. The chip can then be released from the manipulator. The invention also includes systems for utilizing removable nests to align various chip geometries within generic socket designs.
摘要翻译：本发明包括利用可拆卸的机械预处理机构和/或基于光学的精确机构来使芯片在插座内对准的方法。插座可以被配置为使得插座的压缩打开夹紧机构。芯片可以放置在具有操纵器的插座内，并在插座压缩期间对齐。随后，可以释放插座的压缩，同时操纵器保持与芯片接触以将芯片保持就位，直到夹持机构将芯片保持在插座中。然后可以从操纵器释放芯片。本发明还包括用于利用可拆卸嵌套将通用插座设计中的各种芯片几何形状对准的系统。

17. 发明授权

US07122389B2 Method for processing semiconductor devices in a singulated form 失效
标题翻译：用于以单数形式处理半导体器件的方法
公开(公告)号：US07122389B2
公开(公告)日：2006-10-17
申请号：US10920014
申请日：2004-08-16
申请人： Steven L. Hamren , Daniel P. Cram
发明人： Steven L. Hamren , Daniel P. Cram
IPC分类号： G01R31/26
CPC分类号： G01R1/0408 , G01R1/0433 , H01L24/13 , H01L24/16 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/00013 , H01L2924/00014 , H01L2924/01079 , H01L2924/01087 , H01L2924/09701 , H01L2924/14 , H01L2924/16195 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H05K3/321 , H01L2224/29099 , H01L2224/05599
摘要： Improved methods and apparatus are provided for the handling and testing of semiconductor devices. One embodiment comprises a die carrier for one or more semiconductor dice having very fine pitch electrical I/O (input/output) elements. The semiconductor dice are temporarily attached to the die carrier in singulated form to enable testing the dice with conventional contact technology. The die carrier may include a flex circuit base substrate and a rigid support frame. Further embodiments comprise materials and methods for attaching the semiconductor dice to the die carrier and for providing a temporary electrical connection with the semiconductor dice during testing. Exemplary materials for providing the temporary electrical connection may comprise a conductive film or tape, a conductive or conductor-filled epoxy, resin or RTV adhesive-based materials, a water-soluble material impregnated with a conductive filler or non-reflowed solder paste.
摘要翻译：为半导体器件的处理和测试提供了改进的方法和设备。一个实施例包括用于一个或多个具有非常细间距的电I / O（输入/输出）元件的半导体管芯的管芯载体。半导体裸片以单一形式临时附接到模具载体，以便能够用常规接触技术测试骰子。模具载体可以包括柔性电路基底基板和刚性支撑框架。另外的实施例包括用于将半导体管芯附接到管芯载体并用于在测试期间提供与半导体管芯的临时电连接的材料和方法。用于提供临时电连接的示例性材料可以包括导电膜或带，导电或导体填充的环氧树脂或基于RTV粘合剂的材料，浸渍有导电填料或非回流焊膏的水溶性材料。

18. 发明授权

US07121860B2 Pinch-style support contact, method of enabling electrical communication with and supporting an IC package, and socket including same 有权
标题翻译：夹式支持触点，与IC封装进行电气通信和支持的方法以及包括其的插座
公开(公告)号：US07121860B2
公开(公告)日：2006-10-17
申请号：US10933844
申请日：2004-09-02
申请人： Daniel P. Cram , Amos J. Stutzman
发明人： Daniel P. Cram , Amos J. Stutzman
IPC分类号： H01R11/22
CPC分类号： H01R13/62905 , H01R2201/20
摘要： A socket for removably mounting an electronic device and which has utility for testing of the electronic device. The socket includes pinch-style support contacts which establish a reference seating plane for an IC package. The pinch-style support contacts each include a stationary contact arm, a movable contact arm, and a terminal portion. The stationary contact arm and the movable contact arm each include a contact surface configured to contact a terminal of the IC package. The stationary contact arm additionally includes an IC package support surface and extends beyond the height of the movable contact arm. A method of supporting and electrically connecting the socket and IC package is also disclosed.
摘要翻译：一种用于可拆卸地安装电子设备并且具有用于电子设备测试的实用的插座。插座包括捏合式支撑触点，其建立IC封装的参考座平面。夹持式支撑触点各自包括固定触点臂，可动触头臂和端子部分。固定接触臂和可动接触臂各自包括被配置为接触IC封装的端子的接触表面。固定接触臂还包括IC封装支撑表面并延伸超过可动触头臂的高度。还公开了一种支撑和电连接插座和IC封装的方法。

19. 发明授权

US07093622B2 Apparatus for deforming resilient contact structures on semiconductor components 有权
标题翻译：用于使半导体部件上的弹性接触结构变形的装置
公开(公告)号：US07093622B2
公开(公告)日：2006-08-22
申请号：US10893685
申请日：2004-07-16
申请人： Daniel P. Cram
发明人： Daniel P. Cram
IPC分类号： B21F1/02
CPC分类号： G01R1/0408 , G01R31/2831
摘要： A method for testing and burning-in semiconductor components such as semiconductor dice on a semiconductor wafer, is provided. The method includes the step of providing all of the components on the wafer with resilient contact structures, such as metal pins having integral spring segments. The resilient contact structures are used to test the components to identify functional and non-functional components. Following this test, the resilient contact structures on the non-functional components are deformed, such that electrical communication with the non-functional components is prevented in a subsequent burn-in test. This permits the burn-in test to be performed using “shared resources” test equipment. A deformation apparatus for deforming the resilient contact structures includes a deformation block configured to compress, bend or shape the resilient contact structures on the non-functional dice.
摘要翻译：提供了一种用于在半导体晶片上测试和燃烧半导体元件如半导体晶片的方法。该方法包括在晶片上提供具有弹性接触结构的所有部件的步骤，例如具有整体弹簧段的金属销。弹性接触结构用于测试部件以识别功能和非功能部件。在该测试之后，非功能部件上的弹性接触结构变形，从而在随后的老化测试中防止与非功能部件的电连通。这允许使用“共享资源”测试设备执行老化测试。用于使弹性接触结构变形的变形装置包括被配置为压缩，弯曲或成形非功能性骰子上的弹性接触结构的变形块。

20. 发明授权

US07038475B2 Test method for semiconductor components using conductive polymer contact system 失效
标题翻译：使用导电聚合物接触系统的半导体元件的测试方法
公开(公告)号：US07038475B2
公开(公告)日：2006-05-02
申请号：US10667990
申请日：2003-09-22
申请人： Daniel P. Cram
发明人： Daniel P. Cram
IPC分类号： G01R1/073
CPC分类号： G01R1/0735 , G01R1/07378 , H05K1/141 , H05K3/245 , H05K3/326
摘要： A contact system for electrically engaging semiconductor components includes an interface board mountable to an automated test handler, and a floating substrate on the interface board. The interface board includes interface contacts in electrical communication with external test circuitry. The substrate includes flexible segments, and contactors having contact pads on opposing sides of the flexible segments configured to simultaneously electrically engage terminal contacts on the components, and the interface contacts on the interface board. The contact pads include conductive polymer layers that provide an increased compliancy for the contactors. This increased compliancy allows the contactors to accommodate variations in the dimensions and planarity of the terminal contacts on the component. In addition, the substrate includes grooves between the contactors which provide electrical isolation and allow the contactors to move independently of one another. An alternate embodiment contact system includes a Z-axis conductive polymer layer between the substrate and the interface board. Also provided are test methods employing the contact systems.
摘要翻译：用于电接合半导体部件的接触系统包括可安装到自动测试处理器的接口板和接口板上的浮动衬底。接口板包括与外部测试电路进行电气通信的接口触点。衬底包括柔性段，以及接触器，其具有在柔性段的相对侧上的接触焊盘，其被配置为同时电接合部件上的端子触点和接口板上的接口触点。接触垫包括导电聚合物层，其对接触器提供增加的适应性。这种增加的兼容性允许接触器适应组件上的端子触头的尺寸和平面度的变化。此外，衬底包括在接触器之间提供电隔离并允许接触器彼此独立地移动的凹槽。替代实施例的接触系统包括在基板和接口板之间的Z轴导电聚合物层。还提供了使用接触系统的测试方法。

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