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11. 发明授权

US08617949B2 Capacitor and method for making same 有权
标题翻译：电容器及其制作方法
公开(公告)号：US08617949B2
公开(公告)日：2013-12-31
申请号：US13267424
申请日：2011-10-06
申请人： Kuo-Chi Tu , Wen-Chuan Chiang , Chen-Jong Wang
发明人： Kuo-Chi Tu , Wen-Chuan Chiang , Chen-Jong Wang
IPC分类号： H01L21/8242
CPC分类号： H01L28/60 , H01L23/5223 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/10894 , H01L27/11 , H01L27/1116 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A system-on-chip device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, and so forth.
摘要翻译：片上系统装置包括第一区域中的第一电容器，第二区域中的第二电容器，并且还可以包括第三区域中的第三电容器，以及附加区域中的任何附加数量的电容器。电容器可以具有不同的形状和尺寸。区域可以包括多于一个的电容器。区域中的每个电容器具有顶部电极，底部电极和电容器绝缘体。所有电容器的顶部电极以公共工艺形成，而所有电容器的底部电极形成在共同的工艺中。电容器绝缘体可以具有不同数量的亚层，形成不同的材料或厚度。电容器可以形成在层间电介质层中或在金属间介电层中。这些区域可以是混合信号区域，模拟区域等。

12. 发明申请

US20140042590A1 Metal-Insulator-Metal Capacitor and Method of Fabricating 有权
标题翻译：金属绝缘体 - 金属电容器和制造方法
公开(公告)号：US20140042590A1
公开(公告)日：2014-02-13
申请号：US13571441
申请日：2012-08-10
申请人： Kuo-Ji Chen , Wen-Chuan Chiang , Huey-Chi Chu , Ming-Hsiang Song , Chen-Jong Wang
发明人： Kuo-Ji Chen , Wen-Chuan Chiang , Huey-Chi Chu , Ming-Hsiang Song , Chen-Jong Wang
IPC分类号： H01L29/92
CPC分类号： H01L28/60 , H01L28/75 , H01L29/92
摘要： Methods and apparatus are disclosed for manufacturing metal-insulator-metal (MIM) capacitors. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, which has a bottle neck. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, in contact with a sidewall of a via. The sidewall contact or the bottle neck of the electrode may burn out to form a high impedance path when the leakage current exceeds a specification, while the sidewall contact or the bottle neck of the electrode has no impact for normal MIM operations. The MIM capacitors may be used as decoupling capacitors.
摘要翻译：公开了用于制造金属 - 绝缘体 - 金属（MIM）电容器的方法和装置。 MIM电容器可以包括电极，其可以是具有瓶颈的顶部或底部电极。 MIM电容器可以包括与通孔的侧壁接触的电极，其可以是顶部或底部电极。当泄漏电流超过规格时，电极的侧壁接触或瓶颈可燃烧形成高阻抗路径，而电极的侧壁接触或瓶颈对于正常的MIM操作没有影响。 MIM电容器可用作去耦电容器。

13. 发明授权

US09178008B2 Metal-insulator-metal capacitor with current leakage protection 有权
标题翻译：金属绝缘金属电容器，具有漏电保护
公开(公告)号：US09178008B2
公开(公告)日：2015-11-03
申请号：US13571441
申请日：2012-08-10
申请人： Kuo-Ji Chen , Wen-Chuan Chiang , Huey-Chi Chu , Ming-Hsiang Song , Chen-Jong Wang
发明人： Kuo-Ji Chen , Wen-Chuan Chiang , Huey-Chi Chu , Ming-Hsiang Song , Chen-Jong Wang
IPC分类号： H01L49/02 , H01L29/92
CPC分类号： H01L28/60 , H01L28/75 , H01L29/92
摘要： Methods and apparatus are disclosed for manufacturing metal-insulator-metal (MIM) capacitors. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, which has a bottle neck. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, in contact with a sidewall of a via. The sidewall contact or the bottle neck of the electrode may burn out to form a high impedance path when the leakage current exceeds a specification, while the sidewall contact or the bottle neck of the electrode has no impact for normal MIM operations. The MIM capacitors may be used as decoupling capacitors.
摘要翻译：公开了用于制造金属 - 绝缘体 - 金属（MIM）电容器的方法和装置。 MIM电容器可以包括电极，其可以是具有瓶颈的顶部或底部电极。 MIM电容器可以包括与通孔的侧壁接触的电极，其可以是顶部或底部电极。当泄漏电流超过规格时，电极的侧壁接触或瓶颈可燃烧形成高阻抗路径，而电极的侧壁接触或瓶颈对于正常的MIM操作没有影响。 MIM电容器可用作去耦电容器。

14. 发明申请

US20120091559A1 Capacitor and Method for Making Same 有权
标题翻译：电容器和制作方法
公开(公告)号：US20120091559A1
公开(公告)日：2012-04-19
申请号：US13267424
申请日：2011-10-06
申请人： Kuo-Chi Tu , Wen-Chuan Chiang , Chen-Jong Wang
发明人： Kuo-Chi Tu , Wen-Chuan Chiang , Chen-Jong Wang
IPC分类号： H01L21/02 , H01L29/92
CPC分类号： H01L28/60 , H01L23/5223 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/10894 , H01L27/11 , H01L27/1116 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth.
摘要翻译：片上系统（SOC）装置包括第一区域中的第一电容器，第二区域中的第二电容器，以及可以在第三区域中包括第三电容器，以及附加区域中的任何附加数量的电容器。电容器可以具有不同的形状和尺寸。区域可以包括多于一个的电容器。区域中的每个电容器具有顶部电极，底部电极和电容器绝缘体。所有电容器的顶部电极以公共工艺形成，而所有电容器的底部电极形成在共同的工艺中。电容绝缘体可以具有不同数量的子层，形成不同的材料或不同的厚度。电容器可以形成在层间电介质层中或在金属间介电层中。这些区域可以是混合信号区域，模拟区域，射频区域，动态随机存取存储区域等。

15. 发明授权

US06271125B1 Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure 有权
公开(公告)号：US06271125B1
公开(公告)日：2001-08-07
申请号：US09713799
申请日：2000-11-16
申请人： Chue-san Yoo , Chen-Jong Wang , Wen-Chuan Chiang
发明人： Chue-san Yoo , Chen-Jong Wang , Wen-Chuan Chiang
IPC分类号： H01L214763
CPC分类号： H01L21/76877 , H01L21/31116 , H01L21/76816 , H01L27/10855 , H01L27/10888 , H01L27/10897
摘要： A method for reducing the high aspect ratios, encountered when forming, and filling, narrow diameter contact holes, in thick insulator layers, has been developed, featuring a two step contact hole opening and filling procedure. First, lower narrow diameter contact holes are opened in lower levels of insulator layers, then filled with tungsten. After deposition of upper levels of insulator layers, upper narrow diameter contact holes are formed, exposing the tungsten filled, lower diameter contact holes. A second tungsten layer fills the upper, narrow diameter contact hole, resulting in a final narrow diameter contact hole, in thick insulator layers, formed with reduced aspect ratios, via use of the two contact hole openings, and the two tungsten fill procedures. In addition these procedures allow a damascene, tungsten bit line structure, to be formed in a dual shaped opening, in lower insulator layers.

16. 发明授权

US06403416B1 Method for making a double-cylinder-capacitor structure for dynamic random access memory (DRAM) 有权
标题翻译：制造用于动态随机存取存储器（DRAM）的双缸电容器结构的方法
公开(公告)号：US06403416B1
公开(公告)日：2002-06-11
申请号：US09226279
申请日：1999-01-07
申请人： Kuo Ching Huang , Yu-Hua Lee , James (Cheng-Ming) Wu , Wen-Chuan Chiang
发明人： Kuo Ching Huang , Yu-Hua Lee , James (Cheng-Ming) Wu , Wen-Chuan Chiang
IPC分类号： H01L218242
CPC分类号： H01L28/91
摘要： A method using a single masking step for making double-cylinder stacked capacitors for DRAMs which increases capacitance while eliminating erosion of an underlying oxide insulating layer when the masking step is misaligned is described. A planar silicon oxide (SiO2) first insulating layer is formed over device areas, and a first silicon nitride (Si3N4) etch-stop layer is deposited, and openings are etched for capacitor node contacts. A first polysilicon layer is deposited to a thickness sufficient to fill the openings and to form an essentially planar surface. A second insulating layer is deposited and patterned to form portions with vertical sidewalls over the node contacts. A conformal second Si3N4 layer is deposited and etched back to form spacers on the vertical sidewalls, and the first polysilicon layer is etched to the first Si3N4 layer. The second insulating layer is selectively removed using HF acid while the first polysilicon and first Si3N4 layers prevent etching of the underlying first SiO2 layer. A second polysilicon layer is deposited and etched back to form double-cylinder sidewalls for the capacitor bottom electrodes. The first and second Si3N4 layers are removed in hot phosphoric acid. The capacitors are completed by forming an interelectrode dielectric layer on the bottom electrodes, and depositing a third polysilicon layer for top electrodes.
摘要翻译：描述了一种使用单个掩模步骤来制造用于DRAM的双圆柱体堆叠电容器的方法，其在掩蔽步骤未对准时消除了下面的氧化物绝缘层的侵蚀，同时增加了电容。在器件区域上形成平面氧化硅（SiO 2）第一绝缘层，并沉积第一氮化硅（Si 3 N 4）蚀刻停止层，并且蚀刻用于电容器节点接触的开口。第一多晶硅层被沉积到足以填充开口并形成基本平坦的表面的厚度。沉积和图案化第二绝缘层以在节点接触件上形成具有垂直侧壁的部分。沉积保形第二Si 3 N 4层并回蚀刻以在垂直侧壁上形成间隔物，并且将第一多晶硅层蚀刻到第一Si 3 N 4层。使用HF酸选择性地除去第二绝缘层，而第一多晶硅和第一Si 3 N 4层防止蚀刻下面的第一SiO 2层。沉积第二多晶硅层并将其回蚀以形成用于电容器底部电极的双气缸侧壁。在热磷酸中除去第一和第二Si 3 N 4层。电容器通过在底部电极上形成电极间电介质层而形成，并且为顶部电极沉积第三多晶硅层。

17. 发明授权

US5968278A High aspect ratio contact 有权
标题翻译：高宽比接触
公开(公告)号：US5968278A
公开(公告)日：1999-10-19
申请号：US206744
申请日：1998-12-07
申请人： Bao-Ru Young , Chia-Shiung Tsai , Wen-Chuan Chiang
发明人： Bao-Ru Young , Chia-Shiung Tsai , Wen-Chuan Chiang
IPC分类号： H01L21/311 , H01L21/768 , B08B6/00
CPC分类号： H01L21/76816 , H01L21/31138
摘要： An improved etching procedure that uses three processing steps to vastly improve HAR opening profile and improved under-layer selectivity. A new three sequence etching process is provided during which a new three-gas plasma etch is to be used. This new etching sequence is preceded by a new main etch that uses three gasses and followed by a new over-etch procedure that uses the same three gasses and etching conditions as the new main etch.
摘要翻译：改进的蚀刻步骤使用三个加工步骤大大改善HAR开口轮廓和改进的底层选择性。提供了一种新的三序蚀刻工艺，其中将使用新的三气等离子体蚀刻。这个新的蚀刻序列之前是一个新的主要蚀刻，使用三个气体，然后采用与新的主蚀刻相同的三个气体和蚀刻条件的新的过蚀刻程序。

18. 发明授权

US08643074B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08643074B2
公开(公告)日：2014-02-04
申请号：US13462427
申请日：2012-05-02
申请人： Chih-Yang Pai , Kuo-Chi Tu , Wen-Chuan Chiang , Chung-Yen Chou
发明人： Chih-Yang Pai , Kuo-Chi Tu , Wen-Chuan Chiang , Chung-Yen Chou
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , H01L21/76832 , H01L21/76879 , H01L21/76897 , H01L23/5223 , H01L23/5226 , H01L23/53295 , H01L27/108 , H01L27/1085 , H01L27/10855 , H01L27/10894 , H01L28/40 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate, an isolation structure disposed in the semiconductor substrate, a conductive layer disposed over the isolation structure, a capacitor disposed over the isolation structure, the capacitor including a top electrode, a bottom electrode, and a dielectric disposed between the top electrode and the bottom electrode, and a first contact electrically coupling the conductive layer and the bottom electrode, the bottom electrode substantially engaging the first contact on at least two faces.
摘要翻译：半导体器件包括半导体衬底，设置在半导体衬底中的隔离结构，设置在隔离结构上的导电层，设置在隔离结构上的电容器，电容器包括顶部电极，底部电极和介于所述顶部电极和所述底部电极以及将所述导电层和所述底部电极电耦合的第一接触件，所述底部电极在至少两个面上基本接合所述第一接触。

19. 发明授权

US07482278B1 Key-hole free process for high aspect ratio gap filling with reentrant spacer 有权
标题翻译：无缝隙工艺，用于高长宽比间隙填充可重入间隔
公开(公告)号：US07482278B1
公开(公告)日：2009-01-27
申请号：US09247974
申请日：1999-02-11
申请人： Tze-Liang Ying , James (Cheng-Ming) Wu , Yu-Hua Lee , Wen-Chuan Chiang
发明人： Tze-Liang Ying , James (Cheng-Ming) Wu , Yu-Hua Lee , Wen-Chuan Chiang
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/31056 , H01L21/76837
摘要： A new method of depositing PE-oxide or PE-TEOS. An HDP-oxide is provided over a pattern of polysilicon. An etch back is performed to the deposited HDP-oxide, a layer of plasma-enhanced SiN is deposited. This PE-SiN is etched back leaving SiN spacers on the sidewalls of the poly pattern, further leaving a deposition of HDP-oxide on the top surface of the poly pattern. The profile of the holes within the poly pattern in such that the final layer of PE-oxide or PE-TEOS is deposited without resulting in the formation of keyholes in this latter layer.
摘要翻译：一种沉积PE氧化物或PE-TEOS的新方法。在多晶硅图案上提供HDP氧化物。对沉积的HDP-氧化物进行回蚀刻，沉积一层等离子体增强的SiN。该PE-SiN被回蚀刻，留下多边形图案的侧壁上的SiN间隔物，进一步在多晶型图案的顶表面上留下HDP氧化物。多晶型图案中的孔的轮廓使得沉积最终的聚乙烯氧化物层或PE-TEOS层，而不会在后一层中形成键槽。

20. 发明申请

US20080254579A1 Semiconductor device and fabrication thereof 有权
标题翻译：半导体器件及其制造
公开(公告)号：US20080254579A1
公开(公告)日：2008-10-16
申请号：US11785023
申请日：2007-04-13
申请人： Min-Hwa Chi , Wen-Chuan Chiang , Mu-Chi Chiang , Chang-Ku Chen
发明人： Min-Hwa Chi , Wen-Chuan Chiang , Mu-Chi Chiang , Chang-Ku Chen
IPC分类号： H01L21/00 , H01L29/94
CPC分类号： H01L29/665 , H01L29/4991 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833 , Y02P80/30
摘要： A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer. The opening is sealed by a sealing layer to form an air gap.
摘要翻译：公开了一种用于形成半导体器件的方法。提供了包括顺序地形成在其上的栅介电层和栅极电极层的基板。在栅极电介质层和栅极电极层的侧壁上形成偏移间隔物。在间隔物的侧壁上形成碳隔离物，然后除去碳隔离物。使用栅极电极层和偏移间隔物作为掩模，注入衬底以形成轻掺杂区域。该方法还可以包括提供具有顺序地形成在其上的栅极电介质层和栅极电极层的衬底。衬底层形成在栅电极层的侧壁和衬底上。在衬垫层的与栅电极层的侧壁相邻的部分上形成碳隔离物。主间隔件形成在碳隔离件的侧壁上。去除碳间隔物以在衬垫层和主间隔物之间形成开口。开口由密封层密封以形成气隙。

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