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11. 发明授权

US08987086B2 MIM capacitor with lower electrode extending through a conductive layer to an STI 有权
标题翻译： MIM电容器，其下电极延伸穿过导电层至STI
公开(公告)号：US08987086B2
公开(公告)日：2015-03-24
申请号：US13555831
申请日：2012-07-23
申请人： Kuo-Cheng Ching , Kuo-Chi Tu , Chun-Yao Chen
发明人： Kuo-Cheng Ching , Kuo-Chi Tu , Chun-Yao Chen
IPC分类号： H01L29/94 , H01L27/08 , H01L27/06 , H01L27/108 , H01L49/02
CPC分类号： H01L27/0805 , H01L27/0629 , H01L27/10852 , H01L27/10894 , H01L28/91
摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer.
摘要翻译：本公开提供了一种半导体器件，其包括半导体衬底，形成在半导体衬底中的隔离结构，在隔离结构上形成的导电层，以及形成在隔离结构上的金属 - 绝缘体 - 金属（MIM）电容器。 MIM电容器具有冠状形状，其包括顶部电极，第一底部电极和设置在顶部电极和第一底部电极之间的电介质，第一底部电极至少延伸到导电层的顶表面。

12. 发明授权

US07884408B2 One-transistor random access memory technology compatible with metal gate process 有权
标题翻译：单晶体管随机存取技术兼容金属栅极工艺
公开(公告)号：US07884408B2
公开(公告)日：2011-02-08
申请号：US11836710
申请日：2007-08-09
申请人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Chung-Yi Chen , Jian-Yu Shen , Chun-Yao Chen , Hsiang-Fan Lee
发明人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Chung-Yi Chen , Jian-Yu Shen , Chun-Yao Chen , Hsiang-Fan Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/10861 , H01L27/10873
摘要： One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.
摘要翻译：与金属栅极工艺兼容的单晶体管RAM技术制造由与MIM电容器嵌入式隔离结构的顶部电极相同的金属材料形成的金属栅电极。栅极电介质层由与MIM电容器嵌入式隔离结构的电容器电介质相同的高k电介质材料形成。

13. 发明申请

US20080057660A1 Step-gate for a semiconductor device 审中-公开
标题翻译：半导体器件的栅极栅极
公开(公告)号：US20080057660A1
公开(公告)日：2008-03-06
申请号：US11511977
申请日：2006-08-29
申请人： Kuo-Chi Tu , Jai-Hoon Sim , Chun-Yao Chen
发明人： Kuo-Chi Tu , Jai-Hoon Sim , Chun-Yao Chen
IPC分类号： H01L21/20 , H01L21/8242
CPC分类号： H01L27/10873 , H01L27/10885 , H01L29/1037 , H01L29/66636 , H01L29/66787 , H01L29/7835
摘要： A semiconductor device using a recessed step gate. An embodiment comprises a recessed region in a portion of the substrate, a transistor with one source/drain region located within the recessed region and one source/drain region located out of the recessed region, a storage device connected to the source/drain located out of the recessed region, and a bit line connected to the source/drain located within the recessed region.
摘要翻译：一种使用凹陷步进栅极的半导体器件。一个实施例包括在衬底的一部分中的凹陷区域，具有位于凹陷区域内的一个源极/漏极区域和位于凹陷区域外部的一个源极/漏极区域的晶体管，连接到源极/漏极的存储器件以及连接到位于凹陷区域内的源极/漏极的位线。

14. 发明授权

US07282757B2 MIM capacitor structure and method of manufacture 有权
标题翻译： MIM电容器结构及制造方法
公开(公告)号：US07282757B2
公开(公告)日：2007-10-16
申请号：US10689294
申请日：2003-10-20
申请人： Kuo-Chi Tu , Chun-Yao Chen , Shou-Gwo Wuu , Chen-Jong Wang
发明人： Kuo-Chi Tu , Chun-Yao Chen , Shou-Gwo Wuu , Chen-Jong Wang
IPC分类号： H01L27/105
CPC分类号： H01L27/10894 , H01L27/10852 , H01L27/10855 , H01L28/60 , H01L28/91
摘要： A metal-insulator-metal (MIM) capacitor structure and method of manufacturing thereof. A plurality of MIM capacitor patterns is formed in two or more insulating layers. The insulating layers may comprise a via layer and a metallization layer of a semiconductor device. A top portion of the top insulating layer is recessed in a region between at least two adjacent MIM capacitor patterns. When the top plate material of the MIM capacitors is deposited, the top plate material fills the recessed area of the top insulating layer between the adjacent MIM capacitor pattern, forming a connecting region that couples together the top plates of the adjacent MIM capacitors. A portion of the MIM capacitor bottom electrode may be formed in a first metallization layer of the semiconductor device.
摘要翻译：金属绝缘体金属（MIM）电容器结构及其制造方法。多个MIM电容器图案形成在两个或更多个绝缘层中。绝缘层可以包括半导体器件的通孔层和金属化层。顶部绝缘层的顶部凹陷在至少两个相邻的MIM电容器图案之间的区域中。当MIM电容器的顶板材料沉积时，顶板材料填充相邻MIM电容器图案之间的顶部绝缘层的凹陷区域，形成将相邻的MIM电容器的顶板耦合在一起的连接区域。 MIM电容器底部电极的一部分可以形成在半导体器件的第一金属化层中。

15. 发明申请

US20060017115A1 One-transistor random access memory technology compatible with metal gate process 有权
标题翻译：单晶体管随机存取技术兼容金属栅极工艺
公开(公告)号：US20060017115A1
公开(公告)日：2006-01-26
申请号：US10896491
申请日：2004-07-22
申请人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Chung-Yi Chen , C. Shen , Chun-Yao Chen , Hsiang-Fan Lee
发明人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Chung-Yi Chen , C. Shen , Chun-Yao Chen , Hsiang-Fan Lee
IPC分类号： H01L29/76
CPC分类号： H01L27/10861 , H01L27/10873
摘要： One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.
摘要翻译：与金属栅极工艺兼容的单晶体管RAM技术制造由与MIM电容器嵌入式隔离结构的顶部电极相同的金属材料形成的金属栅电极。栅极电介质层由与MIM电容器嵌入式隔离结构的电容器电介质相同的高k电介质材料形成。

16. 发明申请

US20100224925A1 METAL-INSULATOR-METAL STRUCTURE FOR SYSTEM-ON-CHIP TECHNOLOGY 有权
标题翻译：金属绝缘子金属结构系统芯片技术
公开(公告)号：US20100224925A1
公开(公告)日：2010-09-09
申请号：US12397948
申请日：2009-03-04
申请人： Kuo-Cheng Ching , Kuo-Chi Tu , Chun-Yao Chen
发明人： Kuo-Cheng Ching , Kuo-Chi Tu , Chun-Yao Chen
IPC分类号： H01L27/108 , H01L29/92 , H01L21/02
CPC分类号： H01L27/0805 , H01L27/0629 , H01L27/10852 , H01L27/10894 , H01L28/91
摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer.
摘要翻译：本公开提供了一种半导体器件，其包括半导体衬底，形成在半导体衬底中的隔离结构，在隔离结构上形成的导电层，以及形成在隔离结构上的金属 - 绝缘体 - 金属（MIM）电容器。 MIM电容器具有冠状形状，其包括顶部电极，第一底部电极和设置在顶部电极和第一底部电极之间的电介质，第一底部电极至少延伸到导电层的顶表面。

17. 发明授权

US07271083B2 One-transistor random access memory technology compatible with metal gate process 有权
标题翻译：单晶体管随机存取技术兼容金属栅极工艺
公开(公告)号：US07271083B2
公开(公告)日：2007-09-18
申请号：US10896491
申请日：2004-07-22
申请人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Chung-Yi Chen , C. Y. Shen , Chun-Yao Chen , Hsiang-Fan Lee
发明人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Chung-Yi Chen , C. Y. Shen , Chun-Yao Chen , Hsiang-Fan Lee
IPC分类号： H01L29/76
CPC分类号： H01L27/10861 , H01L27/10873
摘要： One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.
摘要翻译：与金属栅极工艺兼容的单晶体管RAM技术制造由与MIM电容器嵌入式隔离结构的顶部电极相同的金属材料形成的金属栅电极。栅极电介质层由与MIM电容器嵌入式隔离结构的电容器电介质相同的高k电介质材料形成。

18. 发明申请

US20050082586A1 MIM capacitor structure and method of manufacture 有权
标题翻译： MIM电容器结构及制造方法
公开(公告)号：US20050082586A1
公开(公告)日：2005-04-21
申请号：US10689294
申请日：2003-10-20
申请人： Kuo-Chi Tu , Chun-Yao Chen , Shou-Gwo Wuu , Chen-Jong Wang
发明人： Kuo-Chi Tu , Chun-Yao Chen , Shou-Gwo Wuu , Chen-Jong Wang
IPC分类号： H01L21/02 , H01L21/8242 , H01L29/76 , H01L21/20
CPC分类号： H01L27/10894 , H01L27/10852 , H01L27/10855 , H01L28/60 , H01L28/91
摘要： A metal-insulator-metal (MIM) capacitor structure and method of manufacturing thereof. A plurality of MIM capacitor patterns is formed in two or more insulating layers. The insulating layers may comprise a via layer and a metallization layer of a semiconductor device. A top portion of the top insulating layer is recessed in a region between at least two adjacent MIM capacitor patterns. When the top plate material of the MIM capacitors is deposited, the top plate material fills the recessed area of the top insulating layer between the adjacent MIM capacitor pattern, forming a connecting region that couples together the top plates of the adjacent MIM capacitors. A portion of the MIM capacitor bottom electrode may be formed in a first metallization layer of the semiconductor device.
摘要翻译：金属绝缘体金属（MIM）电容器结构及其制造方法。多个MIM电容器图案形成在两个或更多个绝缘层中。绝缘层可以包括半导体器件的通孔层和金属化层。顶部绝缘层的顶部凹陷在至少两个相邻的MIM电容器图案之间的区域中。当MIM电容器的顶板材料沉积时，顶板材料填充相邻MIM电容器图案之间的顶部绝缘层的凹陷区域，形成将相邻的MIM电容器的顶板耦合在一起的连接区域。 MIM电容器底部电极的一部分可以形成在半导体器件的第一金属化层中。

19. 发明授权

US06734526B1 Oxidation resistant microelectronics capacitor structure with L shaped isolation spacer 失效
标题翻译：耐氧化微电子电容器结构采用L形隔离间隔器
公开(公告)号：US06734526B1
公开(公告)日：2004-05-11
申请号：US10272648
申请日：2002-10-16
申请人： Kuo-Chi Tu , Yeur-Luen Tu , Tien-Lu Lin , Chun-Yao Chen
发明人： Kuo-Chi Tu , Yeur-Luen Tu , Tien-Lu Lin , Chun-Yao Chen
IPC分类号： H01L2900
CPC分类号： H01L28/57
摘要： A capacitor structure within a microelectronic product employs at least one of: (1) an oxidation barrier layer formed upon a second capacitor plate within the capacitor structure; and (2) a spacer formed adjoining a sidewall of the second capacitor plate, where the spacer is formed with an “L” shape. The foregoing features of the capacitor structure provide a capacitor formed therein with enhanced performance.
摘要翻译：微电子产品中的电容器结构采用以下至少一种：（1）形成在电容器结构内的第二电容器板上的氧化阻挡层; 和（2）与第二电容器板的侧壁邻接的间隔件，其中间隔件形成为“L”形。电容器结构的上述特征提供了在其中形成的具有增强的性能的电容器。

20. 发明授权

US06682982B1 Process method for 1T-SRAM 有权
标题翻译： 1T-SRAM的处理方法
公开(公告)号：US06682982B1
公开(公告)日：2004-01-27
申请号：US10263540
申请日：2002-10-03
申请人： Kuo-Chi Tu , Chun-Yao Chen
发明人： Kuo-Chi Tu , Chun-Yao Chen
IPC分类号： H01L2120
CPC分类号： H01L29/66181 , H01L27/10861 , H01L27/1087 , H01L27/11
摘要： A method of forming a cell memory structure including the step of planarizing an HDP/LDP oxide layer lying over a capacitor area. The method provides for the planarization of the cell storage node, good isolation between the transistor and storage node, reduced step height for the cell-transistor and has the potential for increasing the node capacitance (like DRAM storage node).
摘要翻译：一种形成电池存储结构的方法，包括平面化位于电容器区域上的HDP / LDP氧化物层的步骤。该方法提供了单元存储节点的平面化，晶体管和存储节点之间的良好隔离，降低了单元晶体管的步长，并且具有增加节点电容（如DRAM存储节点）的可能性。

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