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11. 发明申请

US20090085151A1 SEMICONDUCTOR FUSE STRUCTURE AND METHOD 审中-公开
标题翻译：半导体熔丝结构和方法
公开(公告)号：US20090085151A1
公开(公告)日：2009-04-02
申请号：US11863814
申请日：2007-09-28
申请人： Deok-kee Kim , Wai-kin Li , Haining Sam Yang
发明人： Deok-kee Kim , Wai-kin Li , Haining Sam Yang
IPC分类号： H01L29/40 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An electrical structure and method of forming. The electrical structure includes a semiconductor substrate, an insulator layer formed over and in contact with the semiconductor substrate, and a semiconductor fuse structure formed over the insulator layer. The fuse structure includes a silicon layer and a continuous metallic silicide layer. The continuous metallic silicide layer includes a first section formed over and in contact with a first horizontal section of a top surface of the silicon layer, a second section formed over and in contact with a second horizontal section of the top surface of the silicon layer, and a third section formed within an opening within the top surface of the silicon layer.
摘要翻译：一种电气结构和成型方法。电结构包括半导体衬底，形成在半导体衬底上并与半导体衬底接触的绝缘体层，以及形成在绝缘体层上的半导体熔丝结构。熔丝结构包括硅层和连续的金属硅化物层。连续金属硅化物层包括形成在硅层的顶表面的第一水平部分上并与其接触的第一部分，形成在硅层的顶表面的第二水平部分上并与其接触的第二部分，以及形成在所述硅层的顶表面内的开口内的第三部分。

12. 发明授权

US08349723B2 Structure of power grid for semiconductor devices and method of making the same 失效
标题翻译：半导体器件电网结构及其制作方法
公开(公告)号：US08349723B2
公开(公告)日：2013-01-08
申请号：US13342221
申请日：2012-01-03
申请人： Ronald Filippi , Wai-kin Li , Ping-Chuan Wang
发明人： Ronald Filippi , Wai-kin Li , Ping-Chuan Wang
IPC分类号： H01L21/4763
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76847 , H01L21/76852 , H01L23/5286 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.
摘要翻译：本发明的一个实施例提供一种半导体结构，其可以包括形成在电介质层内部的第一导电材料的支柱; 具有底部的第二导电材料的通孔和具有底部的侧壁，并且侧壁被导电衬垫覆盖，并且底部直接形成在螺柱的顶部上并且通过导电衬套与通孔接触; 以及一个或多个第三导电材料的导电路径，所述第三导电材料在所述导电衬套的侧壁处通过所述导电衬套连接到所述通孔。还提供了制造半导体结构的方法。

13. 发明授权

US08299567B2 Structure of metal e-fuse 失效
标题翻译：金属电熔丝的结构
公开(公告)号：US08299567B2
公开(公告)日：2012-10-30
申请号：US12952317
申请日：2010-11-23
申请人： Ping-Chuan Wang , Chunyan E Tian , Ronald Filippi , Wai-kin Li
发明人： Ping-Chuan Wang , Chunyan E Tian , Ronald Filippi , Wai-kin Li
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Structures of electronic fuses (e-fuse) are provided. An un-programmed e-fuse includes a via of a first conductive material having a bottom and sidewalls with a portion of the sidewalls being covered by a conductive liner and the bottom of the via being formed on top of a dielectric layer, and a first and a second conductive path of a second conductive material formed on top of the dielectric layer with the first and second conductive paths being conductively connected through, and only through, the via at the sidewalls. A programmed e-fuse includes a via; a first conductive path at a first side of the via and being separated from sidewalls of the via by a void; and a second conductive path at a second different side of the via and being in conductive contact with the via through sidewalls of the via.
摘要翻译：提供电子保险丝（e-fuse）的结构。未编程的电子熔断器包括具有底部和侧壁的第一导电材料的通孔，侧壁的一部分被导电衬垫覆盖，并且通孔的底部形成在电介质层的顶部上，并且第一以及形成在电介质层顶部上的第二导电材料的第二导电路径，其中第一和第二导电路径通过侧壁导通地连接，并且仅通过通孔。编程的电子熔丝包括通孔; 在通孔的第一侧处的第一导电路径，并且通过空隙与通路的侧壁分离; 以及在所述通孔的第二不同侧的第二导电路径，并且与通孔通过所述通孔的侧壁导电接触。

14. 发明授权

US08164190B2 Structure of power grid for semiconductor devices and method of making the same 有权
标题翻译：半导体器件电网结构及其制作方法
公开(公告)号：US08164190B2
公开(公告)日：2012-04-24
申请号：US12491372
申请日：2009-06-25
申请人： Ronald Filippi , Wai-kin Li , Ping-Chuan Wang
发明人： Ronald Filippi , Wai-kin Li , Ping-Chuan Wang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76847 , H01L21/76852 , H01L23/5286 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.
摘要翻译：本发明的一个实施例提供一种半导体结构，其可以包括形成在电介质层内部的第一导电材料的支柱; 具有底部的第二导电材料的通孔和具有底部的侧壁，并且侧壁被导电衬垫覆盖，并且底部直接形成在螺柱的顶部上并且通过导电衬套与通孔接触; 以及一个或多个第三导电材料的导电路径，所述第三导电材料在所述导电衬套的侧壁处通过导电衬套连接到通孔。还提供了制造半导体结构的方法。

15. 发明申请

US20060110685A1 Apparatus and method to improve resist line roughness in semiconductor wafer processing 审中-公开
标题翻译：改善半导体晶片处理中抗蚀剂线粗糙度的装置和方法
公开(公告)号：US20060110685A1
公开(公告)日：2006-05-25
申请号：US11329991
申请日：2006-01-10
申请人： Wai-kin Li , Rajeev Malik , Joseph Mezzapelle
发明人： Wai-kin Li , Rajeev Malik , Joseph Mezzapelle
IPC分类号： G03F7/00
CPC分类号： G03F7/091 , G03F7/11 , Y10S430/151
摘要： A process for prohibiting amino group transport from the top surface of a layered semiconductor wafer to a photoresist layer introduces a thin film oxynitride over the silicon nitride layer using a high temperature step of nitrous oxide (N2O) plus oxygen (O2) at approximately 300° C. for about 50 to 120 seconds. By oxidizing the silicon nitride layer, the roughness resulting from the adverse affects of amino group transport eliminated. Moreover, this high temperature step, non-plasma process can be used with the more advanced 193 nanometer technology, and is not limited to the 248 nanometer technology. A second method for exposing the silicon nitride layer to an oxidizing ambient, prior to the application of antireflective coating, introduces a mixture of N2H2 and oxygen (O2) ash at a temperature greater than or equal to 250° C. for approximately six minutes. This is followed by an O2 plasma clean and/or an Ozone clean, and then the subsequent layering of the ARC and photoresist.
摘要翻译：用于禁止从层状半导体晶片的顶表面到光致抗蚀剂层的氨基转移的方法使用一氧化二氮（N 2 O 2 O）的高温步骤在氮化硅层上引入薄膜氧氮化物，在约300℃下加氧气（O 2 H 2）约50至120秒。通过氧化氮化硅层，消除了由氨基转移的不利影响产生的粗糙度。此外，这种高温步骤，非等离子体工艺可以采用更先进的193纳米技术，并不限于248纳米技术。在施加抗反射涂层之前，将氮化硅层暴露于氧化环境的第二种方法是引入N 2 H 2 O 2和氧的混合物（O _{2℃）灰分，温度大于或等于250℃约6分钟。之后是等离子体清洁和/或臭氧清洁，然后再分层ARC和光致抗蚀剂。}

16. 发明授权

US09059250B2 Lateral-dimension-reducing metallic hard mask etch 有权
标题翻译：侧向尺寸减小金属硬掩模蚀刻
公开(公告)号：US09059250B2
公开(公告)日：2015-06-16
申请号：US13398875
申请日：2012-02-17
申请人： Samuel S. Choi , Wai-kin Li
发明人： Samuel S. Choi , Wai-kin Li
IPC分类号： H01L21/28 , H01L21/768 , H01L21/033 , H01L21/311 , H01L21/3213
CPC分类号： H01L21/76816 , H01L21/0338 , H01L21/31144 , H01L21/32136 , H01L21/32139
摘要： A combination of gases including at least a fluorocarbon gas, oxygen, and an inert sputter gas is employed to etch at least one opening into an organic photoresist. The amount of oxygen is controlled to a level that limits conversion of a metallic nitride material in an underlying hard mask layer to a metal oxide, and causes organic polymers generated from the organic photoresist to cover peripheral regions of each opening formed in the organic photoresist. The hard mask layer is etched with a taper by the oxygen-limited fluorine-based etch chemistry provided by the combination of gases. The taper angle can be controlled such that a shrink ratio of the lateral dimension by the etch can exceed 2.0.
摘要翻译：使用包括至少一种碳氟化合物气体，氧气和惰性溅射气体的气体的组合来将至少一个开口蚀刻到有机光致抗蚀剂中。将氧的量控制在将下面的硬掩模层中的金属氮化物材料转化为金属氧化物的水平，并且使由有机光致抗蚀剂产生的有机聚合物覆盖在有机光致抗蚀剂中形成的每个开口的周边区域。通过由气体组合提供的受氧限定的氟基蚀刻化学技术，通过锥形蚀刻硬掩模层。可以控制锥角使得通过蚀刻的横向尺寸的收缩率可以超过2.0。

17. 发明申请

US20130214391A1 Lateral-Dimension-Reducing Metallic Hard Mask Etch 有权
标题翻译：侧向尺寸减少金属硬掩模蚀刻
公开(公告)号：US20130214391A1
公开(公告)日：2013-08-22
申请号：US13398875
申请日：2012-02-17
申请人： Samuel S. Choi , Wai-kin Li
发明人： Samuel S. Choi , Wai-kin Li
IPC分类号： H01L29/02 , H01L21/28
CPC分类号： H01L21/76816 , H01L21/0338 , H01L21/31144 , H01L21/32136 , H01L21/32139
摘要： A combination of gases including at least a fluorocarbon gas, oxygen, and an inert sputter gas is employed to etch at least one opening into an organic photoresist. The amount of oxygen is controlled to a level that limits conversion of a metallic nitride material in an underlying hard mask layer to a metal oxide, and causes organic polymers generated from the organic photoresist to cover peripheral regions of each opening formed in the organic photoresist. The hard mask layer is etched with a taper by the oxygen-limited fluorine-based etch chemistry provided by the combination of gases. The taper angle can be controlled such that a shrink ratio of the lateral dimension by the etch can exceed 2.0.
摘要翻译：使用包括至少一种碳氟化合物气体，氧气和惰性溅射气体的气体的组合来将至少一个开口蚀刻到有机光致抗蚀剂中。将氧的量控制在将下面的硬掩模层中的金属氮化物材料转化为金属氧化物的水平，并且使由有机光致抗蚀剂产生的有机聚合物覆盖在有机光致抗蚀剂中形成的每个开口的周边区域。通过由气体组合提供的受氧限定的氟基蚀刻化学技术，通过锥形蚀刻硬掩模层。可以控制锥角使得通过蚀刻的横向尺寸的收缩率可以超过2.0。

18. 发明申请

US20100327445A1 STRUCTURE OF POWER GRID FOR SEMICONDUCTOR DEVICES AND METHOD OF MAKING THE SAME 有权
标题翻译：半导体器件的电源结构及其制造方法
公开(公告)号：US20100327445A1
公开(公告)日：2010-12-30
申请号：US12491372
申请日：2009-06-25
申请人： Ronald Filippi , Wai-kin Li , Ping-Chuan Wang
发明人： Ronald Filippi , Wai-kin Li , Ping-Chuan Wang
IPC分类号： H01L23/535 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76847 , H01L21/76852 , H01L23/5286 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.
摘要翻译：本发明的一个实施例提供一种半导体结构，其可以包括形成在电介质层内部的第一导电材料的支柱; 具有底部的第二导电材料的通孔和具有底部的侧壁，并且侧壁被导电衬垫覆盖，并且底部直接形成在螺柱的顶部上并且通过导电衬套与通孔接触; 以及一个或多个第三导电材料的导电路径，所述第三导电材料在所述导电衬套的侧壁处通过所述导电衬套连接到所述通孔。还提供了制造半导体结构的方法。

19. 发明授权

US07018779B2 Apparatus and method to improve resist line roughness in semiconductor wafer processing 失效
公开(公告)号：US07018779B2
公开(公告)日：2006-03-28
申请号：US10338273
申请日：2003-01-07
申请人： Wai-kin Li , Rajeev Malik , Joseph J. Mezzapelle
发明人： Wai-kin Li , Rajeev Malik , Joseph J. Mezzapelle
IPC分类号： G03F7/00
CPC分类号： G03F7/091 , G03F7/11 , Y10S430/151
摘要： A process for prohibiting amino group transport from the top surface of a layered semiconductor wafer to a photoresist layer introduces a thin film oxynitride over the silicon nitride layer using a high temperature step of nitrous oxide (N2O) plus oxygen (O2) at approximately 300° C. for about 50 to 120 seconds. By oxidizing the silicon nitride layer, the roughness resulting from the adverse affects of amino group transport eliminated. Moreover, this high temperature step, non-plasma process can be used with the more advanced 193 nanometer technology, and is not limited to the 248 nanometer technology. A second method for exposing the silicon nitride layer to an oxidizing ambient, prior to the application of antireflective coating, introduces a mixture of N2H2 and oxygen (O2) ash at a temperature greater than or equal to 250° C. for approximately six minutes. This is followed by an O2 plasma clean and/or an Ozone clean, and then the subsequent layering of the ARC and photoresist.

20. 发明授权

US08361704B2 Method for reducing tip-to-tip spacing between lines 有权
标题翻译：减少线间距尖端间距的方法
公开(公告)号：US08361704B2
公开(公告)日：2013-01-29
申请号：US12352051
申请日：2009-01-12
申请人： Matthew E. Colburn , Wai-kin Li , Haining S. Yang
发明人： Matthew E. Colburn , Wai-kin Li , Haining S. Yang
IPC分类号： G03F7/20
CPC分类号： G03F7/40 , B81C1/00031 , B81C2201/0149 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： This invention provides a method for reducing tip-to-tip spacing between lines using a combination of photolithographic and copolymer self-assembling lithographic techniques. A mask layer is first formed over a substrate with a line structure. A trench opening of a width d is created in the mask layer. A layer of a self-assembling block copolymer is then applied over the mask layer. The block copolymer layer is annealed to form a single unit polymer block of a width or a diameter w which is smaller than d inside the trench opening. The single unit polymer block is selectively removed to form a single opening of a width or a diameter w inside the trench opening. An etch transfer process is performed using the single opening as a mask to form an opening in the line structure in the substrate.
摘要翻译：本发明提供了使用光刻和共聚物自组装光刻技术的组合来减少线之间的尖端到尖端间隔的方法。首先在具有线结构的衬底上形成掩模层。在掩模层中形成宽度为d的沟槽开口。然后将一层自组装嵌段共聚物施加在掩模层上。对嵌段共聚物层进行退火以在沟槽开口内形成宽度或直径w小于d的单一单元聚合物嵌段。选择性地去除单个单元聚合物嵌段以在沟槽开口内形成宽度或直径w的单个开口。使用单个开口作为掩模进行蚀刻转印处理，以在基板中的线结构中形成开口。

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