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11. 发明申请

US20070088873A1 Information processing system 失效
标题翻译：信息处理系统
公开(公告)号：US20070088873A1
公开(公告)日：2007-04-19
申请号：US11511477
申请日：2006-08-29
申请人： Koji Oshikiri , Noriyuki Terao , Junichi Ikeda , Koji Takeo
发明人： Koji Oshikiri , Noriyuki Terao , Junichi Ikeda , Koji Takeo
IPC分类号： G06F3/00
CPC分类号： G06F13/4278 , G06F2213/0026
摘要： An information processing system includes a high-speed serial bus that transmits and receives data independently over communication channels via a tree-structured network including a point-to-point connection, and a control unit that issues a request command based on a request synchronization signal for data with a timing constraint on line synchronous transfer by a line synchronization signal to transmit a plurality of data, including the data with the timing constraint, simultaneously via the high-speed serial bus.
摘要翻译：一种信息处理系统，包括：高速串行总线，其经由包括点对点连接的树结构化网络在通信信道上独立地发送和接收数据;以及控制单元，其基于请求同步信号发出请求命令对于具有通过线路同步信号的线路同步传输的定时约束的数据，以经由高速串行总线同时发送包括具有定时约束的数据的多个数据。

12. 发明申请

US20060173986A1 Communication apparatus, electronic apparatus, imaging apparatus 有权
标题翻译：通信设备，电子设备，成像设备
公开(公告)号：US20060173986A1
公开(公告)日：2006-08-03
申请号：US11327460
申请日：2006-01-09
申请人： Junichi Ikeda , Koji Oshikiri , Koji Takeo , Noriyuki Terao
发明人： Junichi Ikeda , Koji Oshikiri , Koji Takeo , Noriyuki Terao
IPC分类号： G06F15/173
CPC分类号： H04L49/901 , H04L47/10 , H04L47/30 , H04L49/30 , H04L49/90 , H04L2012/5681
摘要： A communication apparatus is disclosed that includes a transmission circuit configured to transmit transmission data to a communication counterpart; a reception circuit configured to receive reception data from the communication counterpart; a storage device configured as at least two buffers including a transmission buffer that stores the transmission data and a reception buffer that stores the reception data; and an address mapping unit configured to perform address mapping of the buffers including the transmission buffer and the reception buffer on the storage device, and adjust the storage capacity of the transmission buffer and the storage capacity of the reception buffer.
摘要翻译：公开了一种通信装置，其包括被配置为向通信对方发送传输数据的传输电路; 接收电路，被配置为从所述通信对方接收接收数据; 配置为包括存储发送数据的发送缓冲器和存储接收数据的接收缓冲器的至少两个缓冲器的存储装置; 以及地址映射单元，被配置为在存储装置上执行包括发送缓冲器和接收缓冲器的缓冲器的地址映射，并且调整发送缓冲器的存储容量和接收缓冲器的存储容量。

13. 发明授权

US07813362B2 Communication apparatus, electronic apparatus, imaging apparatus 有权
标题翻译：通信设备，电子设备，成像设备
公开(公告)号：US07813362B2
公开(公告)日：2010-10-12
申请号：US11327460
申请日：2006-01-09
申请人： Junichi Ikeda , Koji Oshikiri , Koji Takeo , Noriyuki Terao
发明人： Junichi Ikeda , Koji Oshikiri , Koji Takeo , Noriyuki Terao
IPC分类号： H04L12/00
CPC分类号： H04L49/901 , H04L47/10 , H04L47/30 , H04L49/30 , H04L49/90 , H04L2012/5681
摘要： A communication apparatus is disclosed that includes a transmission circuit configured to transmit transmission data to a communication counterpart; a reception circuit configured to receive reception data from the communication counterpart; a storage device configured as at least two buffers including a transmission buffer that stores the transmission data and a reception buffer that stores the reception data; and an address mapping unit configured to perform address mapping of the buffers including the transmission buffer and the reception buffer on the storage device, and adjust the storage capacity of the transmission buffer and the storage capacity of the reception buffer.
摘要翻译：公开了一种通信装置，其包括被配置为向通信对方发送传输数据的传输电路; 接收电路，被配置为从所述通信对方接收接收数据; 配置为包括存储发送数据的发送缓冲器和存储接收数据的接收缓冲器的至少两个缓冲器的存储装置; 以及地址映射单元，被配置为在存储装置上执行包括发送缓冲器和接收缓冲器的缓冲器的地址映射，并且调整发送缓冲器的存储容量和接收缓冲器的存储容量。

14. 发明授权

US07454540B2 Data transferring system and electronic apparatus 失效
标题翻译：数据传输系统和电子设备
公开(公告)号：US07454540B2
公开(公告)日：2008-11-18
申请号：US11332203
申请日：2006-01-17
申请人： Koji Oshikiri , Junichi Ikeda , Koji Takeo , Noriyuki Terao
发明人： Koji Oshikiri , Junichi Ikeda , Koji Takeo , Noriyuki Terao
IPC分类号： G06F3/00
CPC分类号： G06F13/4291 , Y02D10/14 , Y02D10/151
摘要： A data transferring system based on the PCI Express standard in which power saving is realized is disclosed. In the data transferring system, a data transferring device transfers image data based on the PCI Express standard by synchronizing with a line synchronizing signal LSYNC. At this time, the data transferring device causes a period between packets (image data) to be transferred in one line cycle of the line synchronizing signal LSYNC to be shorter than a transition period “t1” which is required to transit from a link state L0 to a link state L0s and from the link state L0s to the link state L0. With this, the number of the transition periods “t1” is reduced and the period of the link state L0s is made long.
摘要翻译：公开了一种基于实现省电的PCI Express标准的数据传输系统。在数据传送系统中，数据传送装置通过与行同步信号LSYNC同步，基于PCI Express标准传送图像数据。此时，数据传送装置使得在行同步信号LSYNC的一个行周期中传送的分组（图像数据）之间的周期短于从链接状态过渡所需的过渡期间“t 1” L 0到链路状态L 0 s，并且从链路状态L 0 s到链路状态L 0。由此，过渡期间“t 1”的数量减少，链路状态L 0 s的周期变长。

15. 发明申请

US20060187944A1 Communication device, data transferring system and electronic apparatus 审中-公开
标题翻译：通信设备，数据传输系统和电子设备
公开(公告)号：US20060187944A1
公开(公告)日：2006-08-24
申请号：US11336863
申请日：2006-01-23
申请人： Koji Takeo , Noriyuki Terao , Junichi Ikeda , Koji Oshikiri
发明人： Koji Takeo , Noriyuki Terao , Junichi Ikeda , Koji Oshikiri
IPC分类号： H04J3/16 , H04L12/56 , H04L12/28 , H04J3/22
CPC分类号： H04L45/00 , H04L45/26
摘要： A data transferring system in which detecting a route from an upper position to a lower position on a tree structure is realized by hardware of communication devices and processes for detecting the above are simplified is disclosed. A root complex broadcasts a search message to a lower node on a tree structure. When a port of the node confirms and receives the search message, the port adds its own information, specifically, the device number of the port, to the data payload part of the search message and sends the search message including the information to a node (end point) located at the lowest position on the tree structure. When the end point receives the search message, the end point sends a reply message to the root complex. The device numbers of the ports where the search message passes through are attached to the reply message.
摘要翻译：通过通信装置的硬件和用于上述检测的处理来实现检测树结构上的上位置到下位置的路由的数据传送系统被简化。根复合体将搜索消息广播到树结构上的下层节点。当节点的端口确认并接收到搜索消息时，端口将其自己的信息，具体地，端口的设备号码添加到搜索消息的数据有效载荷部分，并将包括该信息的搜索消息发送到节点终点）位于树结构的最低位置。当终点接收到搜索消息时，终端向根组合发送回复消息。搜索消息通过的端口的设备号附加到回复消息。

16. 发明授权

US07536489B2 Information processing system for determining payload size based on packet-to-payload size ratio 失效
标题翻译：用于基于分组到有效载荷大小比率来确定有效载荷大小的信息处理系统
公开(公告)号：US07536489B2
公开(公告)日：2009-05-19
申请号：US11511477
申请日：2006-08-29
申请人： Koji Oshikiri , Noriyuki Terao , Junichi Ikeda , Koji Takeo
发明人： Koji Oshikiri , Noriyuki Terao , Junichi Ikeda , Koji Takeo
IPC分类号： H04J3/16 , H04J3/24 , G06F3/00 , G06F5/00
CPC分类号： G06F13/4278 , G06F2213/0026
摘要： An information processing system includes a high-speed serial bus that transmits and receives data independently over communication channels via a tree-structured network including a point-to-point connection, and a control unit that issues a request command based on a request synchronization signal for data with a timing constraint on line synchronous transfer by a line synchronization signal to transmit a plurality of data, including the data with the timing constraint, simultaneously via the high-speed serial bus.
摘要翻译：一种信息处理系统，包括：高速串行总线，其经由包括点对点连接的树结构化网络在通信信道上独立地发送和接收数据;以及控制单元，其基于请求同步信号发出请求命令对于具有通过线路同步信号的线路同步传输的定时约束的数据，以经由高速串行总线同时发送包括具有定时约束的数据的多个数据。

17. 发明申请

US20060209722A1 Data transferring system and electronic apparatus 审中-公开
标题翻译：数据传输系统和电子设备
公开(公告)号：US20060209722A1
公开(公告)日：2006-09-21
申请号：US11327426
申请日：2006-01-09
申请人： Koji Takeo , Noriyuki Terao , Junichi Ikeda , Koji Oshikiri
发明人： Koji Takeo , Noriyuki Terao , Junichi Ikeda , Koji Oshikiri
IPC分类号： H04L12/28
CPC分类号： H04L12/2854
摘要： A data transferring system, in which processes to match settings between devices mutually communicating are simplified, software for the processes is also simplified, and the amount of data to be processed is reduced, is disclosed. In a data transferring system of the PCI Express standard, when settings between facing ports of a switch and an end point are changed, a setting change is transmitted to the port of the end point being one of the facing ports by a configuration request. The port of the end point transmits the setting change to the port of the switch by a message request and the port of the switch executes the setting change. The port of the switch sends a completion message signifying the setting change completion to the port of the end point by a message request. The port of the end point executes the setting change.
摘要翻译：公开了一种数据传送系统，其中相互通信的设备之间的设置匹配的过程被简化，用于处理的软件也被简化，并且减少了要处理的数据量。在PCI Express标准的数据传输系统中，当交换机的相对端口和端点之间的设置发生变化时，通过配置请求将设置更改发送到作为其中一个端口的端点的端口。终端端口通过消息请求将设置更改发送到交换机的端口，交换机的端口执行设置更改。交换机的端口通过消息请求向终端的端口发送表示设置更改完成的完成消息。终点端口执行设置更改。

18. 发明申请

US20060171300A1 Data transferring system and electronic apparatus 失效
标题翻译：数据传输系统和电子设备
公开(公告)号：US20060171300A1
公开(公告)日：2006-08-03
申请号：US11332203
申请日：2006-01-17
申请人： Koji Oshikiri , Junichi Ikeda , Koji Takeo , Noriyuki Terao
发明人： Koji Oshikiri , Junichi Ikeda , Koji Takeo , Noriyuki Terao
IPC分类号： H04J3/14
CPC分类号： G06F13/4291 , Y02D10/14 , Y02D10/151
摘要： A data transferring system based on the PCI Express standard in which power saving is realized is disclosed. In the data transferring system, a data transferring device transfers image data based on the PCI Express standard by synchronizing with a line synchronizing signal LSYNC. At this time, the data transferring device causes a period between packets (image data) to be transferred in one line cycle of the line synchronizing signal LSYNC to be shorter than a transition period “t1” which is required to transit from a link state L0 to a link state L0s and from the link state L0s to the link state L0. With this, the number of the transition periods “t1” is reduced and the period of the link state L0s is made long.
摘要翻译：公开了一种基于实现省电的PCI Express标准的数据传输系统。在数据传送系统中，数据传送装置通过与行同步信号LSYNC同步，基于PCI Express标准传送图像数据。此时，数据传送装置使得在行同步信号LSYNC的一个行周期中传送的分组（图像数据）之间的周期短于从链接状态过渡所需的过渡期间“t 1” L 0到链路状态L 0 s，并且从链路状态L 0 s到链路状态L 0。由此，过渡期间“t 1”的数量减少，链路状态L 0 s的周期变长。

19. 发明授权

US09166933B2 Memory control apparatus, information processing apparatus, and memory control method 有权
标题翻译：存储器控制装置，信息处理装置和存储器控制方法
公开(公告)号：US09166933B2
公开(公告)日：2015-10-20
申请号：US13542139
申请日：2012-07-05
申请人： Satoru Numakura , Junichi Ikeda , Mitsuru Suzuki , Koji Takeo , Tetsuya Satoh , Hiroyuki Takahashi
发明人： Satoru Numakura , Junichi Ikeda , Mitsuru Suzuki , Koji Takeo , Tetsuya Satoh , Hiroyuki Takahashi
IPC分类号： G11C7/10 , H04L12/861 , G11C8/16 , G06F7/00 , H04L12/879
CPC分类号： H04L49/9042 , G06F7/00 , G11C8/16 , H04L49/901
摘要： A memory control apparatus that controls writing and reading of data to/from a memory. The memory control apparatus includes: a sequence control unit that receives a packet sequence including a write packet including a write request of data and a read packet including a read request of the data, and changes an arrangement of the write packet and the read packet included in the packet sequence so that a first predetermined number of write packets are arranged successively and a second predetermined number of read packets are arranged successively; and a command output unit that receives the packet sequence from the sequence control unit, and outputs a write command according to the write packet and an a read command according to the read packet to the memory, in accordance with an order of arrangement of the write packet and the read packet.
摘要翻译：一种用于控制向/从存储器写入和读取数据的存储器控制装置。存储器控制装置包括：序列控制单元，其接收包括包括数据的写入请求的写入包和包含数据的读取请求的读取包的数据包序列，并且改变写入数据包和包含的读取数据包的配置在分组序列中，使得第一预定数量的写分组被连续地排列，并且第二预定数量的读分组被依次布置; 以及命令输出单元，其从顺序控制单元接收分组序列，并且根据写入分组和根据读取的分组的读取命令，根据写入的顺序将顺序输出到存储器包和读包。

20. 发明申请

US20100067042A1 Image forming apparatus and data transferring method 审中-公开
标题翻译：图像形成装置和数据传送方法
公开(公告)号：US20100067042A1
公开(公告)日：2010-03-18
申请号：US12461850
申请日：2009-08-26
申请人： Junichi Ikeda , Koji Oshikiri , Koji Takeo , Tetsuya Sato , Yosuke Kawamura , Hiroyuki Takahashi
发明人： Junichi Ikeda , Koji Oshikiri , Koji Takeo , Tetsuya Sato , Yosuke Kawamura , Hiroyuki Takahashi
IPC分类号： G06F15/00
CPC分类号： H04N1/2307 , H04N1/00912 , H04N1/00933 , H04N1/32 , H04N1/32582 , H04N1/32587 , H04N1/32593 , H04N2201/0082
摘要： A plotter repeats a process of standing by until the next line synchronization timing after data transfer for one line and transferring DMAC control information requesting data transfer for one line to an MCH for each line synchronization timing whereby image data for one page is transferred. Therefore, data transfer from the MCH to the plotter is processed by continuous posted requests, so that float with respect to a line period can be made longer without transmitting a plurality of data transfer requests from the plotter to the MCH in the split method. Thus, a high data transfer performance can be realized with an inexpensive circuit because the cost for mounting a buffer memory or the like on the circuit is not needed.
摘要翻译：绘图仪重复进行直到一行的数据传送之后的下一行同步定时的处理，并且将用于一行的DMAC控制信息请求数据传送到每个行同步定时的MCH，由此传送一页的图像数据。因此，通过连续发送的请求来处理从MCH到绘图机的数据传送，使得可以使得相对于行周期的浮动可以更长，而在分割方法中不将多个数据传送请求从绘图仪发送到MCH。因此，由于不需要在电路上安装缓冲存储器等的成本，所以可以用廉价的电路实现高数据传输性能。

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