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11. 发明授权

US5619674A Multiport cache memory having read-only parts and read-write parts 失效
标题翻译：具有只读部分和读写部分的多端口高速缓存存储器
公开(公告)号：US5619674A
公开(公告)日：1997-04-08
申请号：US294793
申请日：1994-08-24
申请人： Nobuyuki Ikumi
发明人： Nobuyuki Ikumi
IPC分类号： G06F12/08 , G11C8/16 , G11C11/41
CPC分类号： G06F12/0853 , G11C8/16
摘要： A multiport cache memory for exchanging data or instructions with a plurality of arithmetic circuitries independently according to a load instruction or a store instruction provided from a CPU. The cache memory comprises a plurality of read only ports for respectively transmitting data or instructions to each arithmetic circuit according to the load instruction, and a plurality of read/write ports for respectively transmitting the data or the instructions from to each arithmetic circuit according to the load or store instruction.
摘要翻译：用于根据从CPU提供的加载指令或存储指令独立地交换具有多个运算电路的数据或指令的多端口高速缓冲存储器。高速缓存存储器包括多个只读端口，用于根据加载指令分别向每个运算电路发送数据或指令;以及多个读/写端口，用于根据所述加载指令将数据或指令分别从每个运算电路发送加载或存储指令。

12. 发明授权

US5268854A Microprocessor with a function for three-dimensional graphic processing 失效
标题翻译：具有三维图形处理功能的微处理器
公开(公告)号：US5268854A
公开(公告)日：1993-12-07
申请号：US16678
申请日：1993-02-12
申请人： Nobuyuki Ikumi
发明人： Nobuyuki Ikumi
IPC分类号： G06F7/57 , G06F7/38
CPC分类号： G06F7/57 , G06F2207/3828 , G06F2207/3884
摘要： A microprocessor includes an integer processing unit with the decimal point fixed; first and second floating point processing units which can execute simultaneously with the integer processing unit; a register file; a first fixed point processing unit for receiving data at the point n from the register file, for searching for data at the point n+1 by partitioned addition of the increment forwarding by one point, and for outputting the searched data; a second fixed point processing unit for receiving data at the point n from the register file, for searching for data at the point n+2 by partitioned addition of the increment forwarding by two points, and for outputting the searched data; and a merger for receiving the addition results and for gathering data of the bit length of each upper half.
摘要翻译：微处理器包括固定小数点的整数处理单元; 可与整数处理单元同时执行的第一和第二浮点处理单元; 注册档案第一固定点处理单元，用于从所述寄存器文件接收在点n处的数据，用于通过对所述增量转发分一次加1点来搜索在点n + 1处的数据，并输出所搜索的数据; 第二定点处理单元，用于从所述寄存器文件接收在点n处的数据，用于通过将所述递增转发分为两点进行分区加法并在所述点n + 2处搜索数据并输出所搜索的数据; 以及用于接收加法结果并收集每个上半部分的位长度的数据的合并。

13. 发明授权

US4773033A Binary data identification circuit 失效
标题翻译：二进制数据识别电路
公开(公告)号：US4773033A
公开(公告)日：1988-09-20
申请号：US20124
申请日：1987-02-27
申请人： Nobuyuki Ikumi
发明人： Nobuyuki Ikumi
IPC分类号： G06F7/00 , G06F5/01 , G06F7/74 , H03M7/24 , G06F7/38
CPC分类号： G06F7/74 , G06F5/012
摘要： A binary data identification circuit including first and second potential terminals set to first and second logical potential levels, a series circuit including first to (n-1)th transfer gates whose conduction states are controlled responsive to 1st to (n-1)th bit signals of an input operand containing first to nth bit signals, one end of the series circuit being connected to the first potential terminal, nth to (2n-2)th transfer gates which are controlled, responsive to the first to (n-1)th bit signals, so as to have opposite conduction states with respect to those of the first to (n-1)th transfer gates, the nth to (2n-2)th transfer gates being connected at their source to the second potential terminal and at their drain to the drains of the first to (n-1)th transfer gates; and first to nth logic gates whose first input terminals receive the first to nth bit signals and whose second terminals are connected to the first potential terminal and to the drains of the first to (n-1)th transfer gates, the first to nth logic gates generating effective bit data when the first logical level signal is applied to the first and second input terminals thereof.
摘要翻译：一种二进制数据识别电路，包括设置为第一和第二逻辑电位电平的第一和第二电位端子，串联电路，包括第一至第（n-1）个传输门，其导通状态受第1至第（n-1）位包含第一至第n位信号的输入操作数的信号，串联电路的一端连接到第一电位端，第n至第（2n-2）个传输门，其被控制，响应于第一至第（n-1）第（n-1）个传输门，其第n至第（2n-2）个传输门在其源极连接到第二电位端，并且在排水到第一至第（n-1）个转运大门的排水沟处; 以及第一至第n逻辑门，其第一输入端接收第一至第n位信号，其第二端连接到第一至第（n-1）传输门的第一电位端和漏极，第一至第n逻辑当第一逻辑电平信号被施加到其第一和第二输入端时，门产生有效位数据。

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