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11. 发明授权

US08344441B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US08344441B2
公开(公告)日：2013-01-01
申请号：US12839723
申请日：2010-07-20
申请人： Kiyohito Nishihara
发明人： Kiyohito Nishihara
IPC分类号： H01L29/788
CPC分类号： H01L21/76819 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11565 , H01L27/11568
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: a semiconductor substrate; an element isolation insulator formed in an upper portion of the semiconductor substrate and dividing the upper portion into first and second active areas extending in a first direction; a first contact connected to the first active area; and a second contact connected to the second active area. Each of the first and second active area includes: a first portion connected to one of the first contact and the second contact; and a second portion having an upper surface being placed lower than an upper surface of the first portion. The first contact and the second contact are mutually shifted in the first direction. The first portion of the first active area is disposed adjacent to the second portion of the second active area.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括：半导体衬底; 形成在所述半导体衬底的上部并将所述上部分割成沿第一方向延伸的第一和第二有源区的元件绝缘绝缘体; 连接到第一活动区域的第一触点; 以及连接到第二活动区域的第二触点。第一和第二有效区域中的每一个包括：连接到第一接触件和第二接触件之一的第一部件; 以及第二部分，其具有比第一部分的上表面低的上表面。第一触点和第二触点在第一方向相互移位。第一有效区域的第一部分被布置成与第二有效区域的第二部分相邻。

12. 发明申请

US20120018780A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120018780A1
公开(公告)日：2012-01-26
申请号：US13075665
申请日：2011-03-30
申请人： Kazuaki Iwasawa , Shigeo Kondo , Hiroshi Akahori , Kiyohito Nishihara , Yingkang Zhang , Masaki Kondo , Hidenobu Nagashima , Takashi Ichikawa
发明人： Kazuaki Iwasawa , Shigeo Kondo , Hiroshi Akahori , Kiyohito Nishihara , Yingkang Zhang , Masaki Kondo , Hidenobu Nagashima , Takashi Ichikawa
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L27/11521
摘要： According to one embodiment, a method is disclosed for manufacturing a semiconductor device. A side face parallel to a channel direction of a plurality of gate electrodes provided via a gate insulating film above a semiconductor substrate is included as a part of an inner wall of an isolation groove provided between the adjacent gate electrodes. The method can include forming a protection film covering the side face of the gate electrode. The method can include etching the semiconductor substrate using the gate electrode as a mask to form the isolation groove. The side face of the gate electrode is covered with the protection film. The method can include forming a first insulating film by oxidizing a surface of the isolation groove to fill a bottom portion of the isolation groove. In addition, the method can include forming a second insulating film on the first insulating film to fill an upper portion of the isolation groove including the side face of the gate electrode.
摘要翻译：根据一个实施例，公开了一种用于制造半导体器件的方法。作为设置在相邻栅电极之间的隔离槽的内壁的一部分，包括平行于通过半导体基板上方的栅极绝缘膜设置的多个栅电极的沟道方向的侧面。该方法可以包括形成覆盖栅电极的侧面的保护膜。该方法可以包括使用栅电极作为掩模来蚀刻半导体衬底以形成隔离槽。栅电极的侧面被保护膜覆盖。该方法可以包括通过氧化隔离槽的表面来填充隔离槽的底部来形成第一绝缘膜。此外，该方法可以包括在第一绝缘膜上形成第二绝缘膜以填充包括栅电极的侧面的隔离槽的上部。

13. 发明授权

US07986000B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07986000B2
公开(公告)日：2011-07-26
申请号：US12564349
申请日：2009-09-22
申请人： Makoto Mizukami , Kiyohito Nishihara , Masaki Kondo , Takashi Izumida , Hirokazu Ishida , Atsushi Fukumoto , Fumiki Aiso , Daigo Ichinose , Tadashi Iguchi
发明人： Makoto Mizukami , Kiyohito Nishihara , Masaki Kondo , Takashi Izumida , Hirokazu Ishida , Atsushi Fukumoto , Fumiki Aiso , Daigo Ichinose , Tadashi Iguchi
IPC分类号： H01L29/76 , H01L21/00 , H01L21/84
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/11521 , H01L27/11524
摘要： A semiconductor device is formed on a SOI substrate having a semiconductor substrate, a buried oxide film formed on the semiconductor substrate, and a semiconductor layer formed on the buried oxide film, the semiconductor substrate having a first conductive type, the semiconductor layer having a second conductive type, wherein the buried oxide film has a first opening opened therethrough for communicating the semiconductor substrate with the semiconductor layer, the semiconductor layer is arranged to have a first buried portion buried in the first opening in contact with the semiconductor substrate and a semiconductor layer main portion positioned on the first buried portion and on the buried oxide film, the semiconductor substrate has a connection layer buried in a surface of the semiconductor substrate and electrically connected to the first buried portion in the first opening, the connection layer having the second conductive type, and the semiconductor device includes a contact electrode buried in a second opening, a side surface of the contact electrode being connected to the semiconductor layer main portion, a bottom surface of the contact electrode being connected to the connection layer, the second opening passing through the semiconductor layer main portion and the buried oxide film, and the second opening reaching a surface portion of the connection layer.
摘要翻译：半导体器件形成在具有半导体衬底的SOI衬底上，形成在半导体衬底上的掩埋氧化膜以及形成在掩埋氧化膜上的半导体层，该半导体衬底具有第一导电类型，该半导体层具有第二导电型导电型，其中所述掩埋氧化物膜具有通过其开口的第一开口，用于使所述半导体衬底与所述半导体层连通，所述半导体层被布置为具有埋在所述第一开口中的与所述半导体衬底接触的第一掩埋部分和半导体层主要部分位于第一掩埋部分和掩埋氧化膜上，半导体衬底具有埋在半导体衬底的表面中并与第一开口中的第一掩埋部分电连接的连接层，连接层具有第二导电类型，并且半导体器件包括接触电极阴极埋入第二开口中，接触电极的侧表面连接到半导体层主体部分，接触电极的底表面连接到连接层，第二开口穿过半导体层主体部分和埋设氧化膜，第二开口到达连接层的表面部分。

14. 发明授权

US07928516B2 Semiconductor storage device and manufacturing method thereof 失效
标题翻译：半导体存储装置及其制造方法
公开(公告)号：US07928516B2
公开(公告)日：2011-04-19
申请号：US12276815
申请日：2008-11-24
申请人： Kiyohito Nishihara
发明人： Kiyohito Nishihara
IPC分类号： H01L29/76
CPC分类号： H01L21/84 , H01L27/11521 , H01L27/11524 , H01L27/1203
摘要： A semiconductor storage device include a semiconductor substrate, an insulating layer provided on the semiconductor substrate and having an opening, a semiconductor layer provided on the insulating layer, the semiconductor layer having a recess at a center of a surface thereof above the opening, a memory cell unit provided on the semiconductor layer and including a plurality of memory cells, current paths of the memory cells being connected in series, a selecting transistor adjacent to the memory cell unit and arranged on a region of the semiconductor layer including the recess, the selecting transistor including a gate insulating film provided on the region of the semiconductor layer including the recess and a gate electrode provided on the gate insulating film.
摘要翻译：半导体存储装置包括半导体基板，设置在半导体基板上的具有开口的绝缘层，设置在绝缘层上的半导体层，半导体层在开口上方的表面的中心具有凹部，存储器单元单元，设置在所述半导体层上并且包括多个存储单元，所述存储单元的电流路径串联连接，所述选择晶体管与所述存储单元单元相邻并且布置在包括所述凹部的所述半导体层的区域上，所述选择晶体管，其包括设置在包括凹部的半导体层的区域上的栅极绝缘膜和设置在栅极绝缘膜上的栅电极。

15. 发明申请

US20100133627A1 DEPLETION-TYPE NAND FLASH MEMORY 有权
标题翻译： DEPLETION型NAND闪存
公开(公告)号：US20100133627A1
公开(公告)日：2010-06-03
申请号：US12603099
申请日：2009-10-21
申请人： Makoto Mizukami , Kiyohito Nishihara
发明人： Makoto Mizukami , Kiyohito Nishihara
IPC分类号： H01L27/088
CPC分类号： H01L27/11568 , G11C16/0483 , H01L21/84 , H01L27/11521 , H01L27/11524 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L27/1203
摘要： A depletion-type NAND flash memory includes a NAND string composed of a plurality of serially connected FETs, a control circuit which controls gate potentials of the plurality of FETs in a read operation, a particular potential storage, and an adjacent memory cell threshold storage, wherein each of the plurality of FETs is a transistor whose threshold changes in accordance with a charge quantity in a charge accumulation layer, the adjacent memory cell threshold storage stores a threshold of a source line side FET adjacent to a source line side of a selected FET, and the control circuit applies a potential to the gate electrode of the source line side FET in the read operation, the applied potential being obtained by adding a particular potential stored in the particular potential storage to a threshold stored in the adjacent memory cell threshold storage.
摘要翻译：耗尽型NAND闪存包括由多个串联连接的FET组成的NAND串，控制电路，其在读取操作中控制多个FET的栅极电位，特定的电位存储器和相邻的存储单元阈值存储器，其中，所述多个FET中的每一个是其阈值根据电荷累积层中的电荷量而变化的晶体管，所述相邻存储单元阈值存储器存储与所选择的FET的源极侧相邻的源极侧FET的阈值，并且控制电路在读取操作中向源极侧FET的栅电极施加电位，所施加的电位通过将存储在特定电位存储器中的特定电位加到存储在相邻存储单元阈值存储器中的阈值。

16. 发明授权

US08890105B2 Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US08890105B2
公开(公告)日：2014-11-18
申请号：US13687737
申请日：2012-11-28
申请人： Kiyohito Nishihara
发明人： Kiyohito Nishihara
IPC分类号： H01L29/02 , H01L45/00 , H01L27/24
CPC分类号： H01L45/00 , H01L27/2481 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1266 , H01L45/1273 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/1675
摘要： A nonvolatile memory according to an embodiment includes a first wiring line; a second wiring line arranged above the first wiring line and extending in a direction crossing the first wiring line; and a resistance change layer arranged in an intersection region of the first wiring line the second wiring line, the second wiring line including a first member extending in the direction in which the second wiring line extends, and an electrode layer containing a metal element arranged on a side surface of the first member along the direction in which the second wiring line extends, a lower surface of the electrode layer being in contact with an upper surface of the resistance change layer.
摘要翻译：根据实施例的非易失性存储器包括第一布线; 布置在所述第一布线之上并沿与所述第一布线相交的方向延伸的第二布线; 以及电阻变化层，其布置在所述第一布线与所述第二布线的交叉区域中，所述第二布线包括沿着所述第二布线延伸的方向延伸的第一构件和包含布置在所述第二布线上的金属元件的电极层第一构件的沿着第二布线延伸的方向的侧表面，电极层的下表面与电阻变化层的上表面接触。

17. 发明授权

US08421234B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08421234B2
公开(公告)日：2013-04-16
申请号：US12833329
申请日：2010-07-09
申请人： Kiyohito Nishihara
发明人： Kiyohito Nishihara
IPC分类号： H01L23/48
CPC分类号： H01L21/76816 , H01L21/76843 , H01L21/76885 , H01L21/76897 , H01L23/485 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11565 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to an embodiment of the present invention includes a substrate, isolation layers and active regions formed in the substrate, and arranged alternately along a first direction parallel to a surface of the substrate, an inter layer dielectric formed on the isolation layers and the active regions, and having holes for respective contact plugs on the respective active regions, barrier layers formed in the holes, each of the barrier layers being formed on a top surface of an active region exposed in a hole and on one of two side surfaces of the hole, the two side surfaces of the hole being perpendicular to the first direction, and plug material layers formed on the barrier layers in the holes.
摘要翻译：根据本发明的实施例的半导体器件包括衬底，隔离层和形成在衬底中的有源区，并且沿着平行于衬底的表面的第一方向交替排列，形成在隔离层上的层间电介质和有源区，并且在各个有源区上具有用于相应接触插塞的孔，形成在孔中的阻挡层，每个阻挡层形成在暴露在孔中的有源区的顶表面和两个侧表面之一所述孔的两个侧表面垂直于所述第一方向，并且所述塞材料层形成在所述孔中的阻挡层上。

18. 发明申请

US20100117135A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100117135A1
公开(公告)日：2010-05-13
申请号：US12564349
申请日：2009-09-22
申请人： Makoto MIZUKAMI , Kiyohito Nishihara , Masaki Kondo , Takashi Izumida , Hirokazu Ishida , Atsushi Fukumoto , Fumiki Aiso , Daigo Ichinose , Tadashi Iguchi
发明人： Makoto MIZUKAMI , Kiyohito Nishihara , Masaki Kondo , Takashi Izumida , Hirokazu Ishida , Atsushi Fukumoto , Fumiki Aiso , Daigo Ichinose , Tadashi Iguchi
IPC分类号： H01L27/12 , H01L21/86
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/11521 , H01L27/11524
摘要： A semiconductor device is formed on a SOI substrate having a semiconductor substrate, a buried oxide film formed on the semiconductor substrate, and a semiconductor layer formed on the buried oxide film, the semiconductor substrate having a first conductive type, the semiconductor layer having a second conductive type, wherein the buried oxide film has a first opening opened therethrough for communicating the semiconductor substrate with the semiconductor layer, the semiconductor layer is arranged to have a first buried portion buried in the first opening in contact with the semiconductor substrate and a semiconductor layer main portion positioned on the first buried portion and on the buried oxide film, the semiconductor substrate has a connection layer buried in a surface of the semiconductor substrate and electrically connected to the first buried portion in the first opening, the connection layer having the second conductive type, and the semiconductor device includes a contact electrode buried in a second opening, a side surface of the contact electrode being connected to the semiconductor layer main portion, a bottom surface of the contact electrode being connected to the connection layer, the second opening passing through the semiconductor layer main portion and the buried oxide film, and the second opening reaching a surface portion of the connection layer.
摘要翻译：半导体器件形成在具有半导体衬底的SOI衬底上，形成在半导体衬底上的掩埋氧化膜以及形成在掩埋氧化膜上的半导体层，该半导体衬底具有第一导电类型，该半导体层具有第二导电型导电型，其中所述掩埋氧化物膜具有通过其开口的第一开口，用于使所述半导体衬底与所述半导体层连通，所述半导体层被布置为具有埋在所述第一开口中的与所述半导体衬底接触的第一掩埋部分和半导体层主要部分位于第一掩埋部分和掩埋氧化膜上，半导体衬底具有埋在半导体衬底的表面中并与第一开口中的第一掩埋部分电连接的连接层，连接层具有第二导电类型，并且半导体器件包括接触电极阴极埋入第二开口中，接触电极的侧表面连接到半导体层主体部分，接触电极的底表面连接到连接层，第二开口穿过半导体层主体部分和埋设氧化膜，第二开口到达连接层的表面部分。

19. 发明授权

US08969998B2 NAND type nonvolatile semiconductor memory device and method for manufacturing same 有权
标题翻译： NAND型非易失性半导体存储器件及其制造方法
公开(公告)号：US08969998B2
公开(公告)日：2015-03-03
申请号：US13225743
申请日：2011-09-06
申请人： Kiyohito Nishihara
发明人： Kiyohito Nishihara
IPC分类号： H01L21/70 , H01L27/115 , H01L21/762 , H01L23/485
CPC分类号： H01L27/11524 , H01L21/76229 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a plurality of element-separating insulators, and contacts. The plurality of element-separating insulators partition the upper layer portion into a plurality of active areas extending in a first direction. The contacts are connected to the active areas. A recess is made in a part in the first direction of an upper surface of each of the active areas. The recess is made across the entire active area in a second direction orthogonal to the first direction. Positions in the first direction of two of the contacts connected respectively to mutually-adjacent active areas are different from each other. One of the contacts is in contact with a side surface of the recess and not in contact with a bottom surface of the recess.
摘要翻译：根据一个实施例，半导体存储器件包括半导体衬底，多个元件分离绝缘体和触点。多个元件分离绝缘体将上层部分分成沿第一方向延伸的多个有效区域。触点连接到活动区域。在每个有源区域的上表面的第一方向上的部分中形成凹部。在与第一方向正交的第二方向上在整个有源区域上形成凹部。在相互相邻的有源区域分别连接的两个触点的第一方向上的位置彼此不同。触点之一与凹部的侧表面接触并且不与凹部的底表面接触。

20. 发明授权

US08723245B2 Nonvolatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US08723245B2
公开(公告)日：2014-05-13
申请号：US13052531
申请日：2011-03-21
申请人： Hiroshi Akahori , Kiyohito Nishihara , Masaki Kondo , Yingkang Zhang , Shigeo Kondo , Hidenobu Nagashima , Kazuaki Iwasawa , Takashi Ichikawa
发明人： Hiroshi Akahori , Kiyohito Nishihara , Masaki Kondo , Yingkang Zhang , Shigeo Kondo , Hidenobu Nagashima , Kazuaki Iwasawa , Takashi Ichikawa
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L27/11521
摘要： According to one embodiment, a nonvolatile memory device includes a substrate, first and second tunnel insulating films, first and second floating gate electrodes, an intergate insulating film and a control gate electrode. The substrate has first and second active regions isolated from each other by an element isolation trench. The first and second tunnel insulating films are located in the first and second active regions, respectively. The first and second floating gate electrodes are located on the first and second tunnel insulating films, respectively. The intergate insulating film includes a first insulating layer of a first insulating material, an electron trap layer of a second insulating material on the first insulating layer, and a second insulating layer of the first insulating material on the electron trap layer. The control gate electrode is located on the intergate insulating film.
摘要翻译：根据一个实施例，非易失性存储器件包括衬底，第一和第二隧道绝缘膜，第一和第二浮栅电极，栅间绝缘膜和控制栅电极。衬底具有通过元件隔离沟槽彼此隔离的第一和第二有源区。第一和第二隧道绝缘膜分别位于第一和第二有源区中。第一和第二浮栅电极分别位于第一和第二隧道绝缘膜上。隔间绝缘膜包括第一绝缘材料的第一绝缘层，第一绝缘层上的第二绝缘材料的电子陷阱层和电子陷阱层上的第一绝缘材料的第二绝缘层。控制栅电极位于隔间绝缘膜上。

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