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11. 发明申请

US20090186474A1 Nonvolatile semiconductor storage device and manufacturing method therefor 有权
公开(公告)号：US20090186474A1
公开(公告)日：2009-07-23
申请号：US12318493
申请日：2008-12-30
申请人： Hiroshi Watanabe , Atsuhiro Kinoshita , Akira Takashima , Daisuke Hagishima
发明人： Hiroshi Watanabe , Atsuhiro Kinoshita , Akira Takashima , Daisuke Hagishima
IPC分类号： H01L21/302
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A nonvolatile semiconductor storage device includes a semiconductor substrate; a plurality of isolation regions formed in the semiconductor substrate; an element-forming region formed between adjacent isolation regions; a first gate insulating film provided on the element-forming region; a floating gate electrode which is provided on the first gate insulating film and in which a width of a lower hem facing the element-forming region is narrower than a width of the element-forming region in a section taken in a direction perpendicular to a direction in which the isolation regions extend; a second gate insulating film provided on the floating gate electrode; and a control gate electrode provided on the second gate insulating film.

12. 发明申请

US20130307054A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20130307054A1
公开(公告)日：2013-11-21
申请号：US13606292
申请日：2012-09-07
申请人： Shinichi YASUDA , Kosuke Tatsumura , Mari Matsumoto , Koichiro Zaitsu , Masato Oda , Atsuhiro Kinoshita , Daisuke Hagishima , Yoshifumi Nishi , Takahiro Kurita , Shinobu Fujita
发明人： Shinichi YASUDA , Kosuke Tatsumura , Mari Matsumoto , Koichiro Zaitsu , Masato Oda , Atsuhiro Kinoshita , Daisuke Hagishima , Yoshifumi Nishi , Takahiro Kurita , Shinobu Fujita
IPC分类号： H01L27/105
CPC分类号： G11C16/10 , H01L21/823456 , H01L21/823462 , H01L27/11526 , H01L27/11573 , H01L29/7881 , H01L29/792
摘要： One embodiment provides a semiconductor integrated circuit, including: a substrate; a plurality of nonvolatile memory portions formed in the substrate, each including a first nonvolatile memory and a second nonvolatile memory; and a plurality of logic transistor portions formed in the substrate, each including at least one of logic transistor, wherein the logic transistors include: a first transistor which is directly connected to drains of the first and second nonvolatile memories at its gate; and a second transistor which is not directly connected to the drains of the first and second nonvolatile memories, and wherein a bottom surface of the gate of each of the logic transistors sandwiching the first and second nonvolatile memories is lower in height from a top surface of the substrate than a bottom surface of the control gate of each of the first and second nonvolatile memories.
摘要翻译：一个实施例提供一种半导体集成电路，包括：基板; 形成在所述基板中的多个非易失性存储部，每个包括第一非易失性存储器和第二非易失性存储器; 以及形成在所述衬底中的多个逻辑晶体管部分，每个逻辑晶体管部分包括逻辑晶体管中的至少一个，其中所述逻辑晶体管包括：第一晶体管，其第一和第二非易失性存储器的栅极直接连接到第一晶体管; 以及第二晶体管，其不直接连接到第一和第二非易失性存储器的漏极，并且其中夹着第一和第二非易失性存储器的每个逻辑晶体管的栅极的底表面的高度与所述基板比所述第一和第二非易失性存储器中的每一个的所述控制栅极的底表面。

13. 发明授权

US08525251B2 Nonvolatile programmable logic switch 失效
标题翻译：非易失性可编程逻辑开关
公开(公告)号：US08525251B2
公开(公告)日：2013-09-03
申请号：US13221292
申请日：2011-08-30
申请人： Daisuke Hagishima , Atsuhiro Kinoshita , Kazuya Matsuzawa , Kazutaka Ikegami , Yoshifumi Nishi
发明人： Daisuke Hagishima , Atsuhiro Kinoshita , Kazuya Matsuzawa , Kazutaka Ikegami , Yoshifumi Nishi
IPC分类号： H01L29/792
CPC分类号： H01L29/7881 , G11C16/0408 , H01L27/1052 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L27/11807 , H01L29/66825
摘要： A nonvolatile programmable logic switch according to an embodiment includes: a memory cell transistor including: a first source region and a first drain region of a second conductivity type formed at a distance from each other in a first semiconductor region of a first conductivity type; a first insulating film, a charge storage film, a second insulating film, and a control gate stacked in this order and formed on the first semiconductor region between the first source region and the first drain region; a pass transistor including: a second source region and a second drain region of a second conductivity type formed at a distance from each other in a second semiconductor region of the first conductivity type; a third insulating film, a gate electrode stacked in this order and formed on the second semiconductor region between the second source region and the second drain region, the gate electrode being electrically connected to the first drain region; and an electrode for applying a substrate bias to the first and second semiconductor regions.
摘要翻译：根据实施例的非易失性可编程逻辑开关包括：存储单元晶体管，包括：在第一导电类型的第一半导体区域中彼此间隔开形成的第二导电类型的第一源极区域和第一漏极区域; 第一绝缘膜，电荷存储膜，第二绝缘膜和控制栅极，并且形成在第一源极区域和第一漏极区域之间的第一半导体区域上; 传输晶体管，包括：在第一导电类型的第二半导体区域中彼此成一定距离地形成的第二导电类型的第二源极区域和第二漏极区域; 第三绝缘膜，栅极电极，并且形成在第二源极区域和第二漏极区域之间的第二半导体区域上，栅极电连接到第一漏极区域; 以及用于将衬底偏压施加到第一和第二半导体区域的电极。

14. 发明授权

US07489006B2 Nonvolatile semiconductor storage device and manufacturing method therefor 失效
标题翻译：非易失性半导体存储装置及其制造方法
公开(公告)号：US07489006B2
公开(公告)日：2009-02-10
申请号：US11224049
申请日：2005-09-13
申请人： Hiroshi Watanabe , Atsuhiro Kinoshita , Akira Takashima , Daisuke Hagishima
发明人： Hiroshi Watanabe , Atsuhiro Kinoshita , Akira Takashima , Daisuke Hagishima
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A nonvolatile semiconductor storage device includes a semiconductor substrate; a plurality of isolation regions formed in the semiconductor substrate; an element-forming region formed between adjacent isolation regions; a first gate insulating film provided on the element-forming region; a floating gate electrode which is provided on the first gate insulating film and in which a width of a lower hem facing the element-forming region is narrower than a width of the element-forming region in a section taken in a direction perpendicular to a direction in which the isolation regions extend; a second gate insulating film provided on the floating gate electrode; and a control gate electrode provided on the second gate insulating film.
摘要翻译：非易失性半导体存储器件包括半导体衬底; 形成在所述半导体衬底中的多个隔离区; 在相邻隔离区域之间形成的元件形成区域; 设置在元件形成区域上的第一栅极绝缘膜; 设置在第一栅极绝缘膜上并且面向元件形成区域的下边缘的宽度比沿着与方向垂直的方向截取的截面中的元件形成区域的宽度窄的浮栅电极其中隔离区域延伸; 设置在所述浮栅电极上的第二栅极绝缘膜; 以及设置在第二栅极绝缘膜上的控制栅电极。

15. 发明申请

US20090020803A1 AGING DEVICE 有权
标题翻译：老化设备
公开(公告)号：US20090020803A1
公开(公告)日：2009-01-22
申请号：US12173535
申请日：2008-07-15
申请人： Hiroshi Watanabe , Atsuhiro Kinoshita , Shigeki Kobayashi , Daisuke Hagishima
发明人： Hiroshi Watanabe , Atsuhiro Kinoshita , Shigeki Kobayashi , Daisuke Hagishima
IPC分类号： H01L29/788
CPC分类号： G04F10/10 , G11C16/0408 , G11C2216/10 , H01L21/28273 , H01L27/115 , H01L27/11558 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： An aging device according to an embodiment of the present invention includes a semiconductor substrate, first and second diffusion layers provided in a first element region, a floating gate provided above a channel region between the first and second diffusion layers, and a control gate electrode provided beside the floating gate with an interval in the lateral direction. A coupling capacitance between the floating gate and the control gate electrode is larger than a coupling capacitance between the floating gate and the semiconductor substrate.
摘要翻译：根据本发明的实施例的老化装置包括半导体衬底，设置在第一元件区域中的第一和第二扩散层，设置在第一和第二扩散层之间的沟道区域上方的浮动栅极和设置在第一和第二扩散层之间的控制栅电极在浮动门旁边，横向间隔一段距离。浮置栅极和控制栅电极之间的耦合电容大于浮置栅极和半导体衬底之间的耦合电容。

16. 发明授权

US06992358B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06992358B2
公开(公告)日：2006-01-31
申请号：US10874732
申请日：2004-06-24
申请人： Katsuhiko Hieda , Kazuya Matsuzawa , Daisuke Hagishima
发明人： Katsuhiko Hieda , Kazuya Matsuzawa , Daisuke Hagishima
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L27/108 , H01L27/10814 , H01L27/10829 , H01L27/10873 , H01L27/10879 , H01L27/1211 , H01L29/42392 , H01L29/66545 , H01L29/66795 , H01L29/7854 , H01L29/78648
摘要： Disclosed is a semiconductor device comprising an underlying insulating film having a depression, a semiconductor structure which includes a first semiconductor portion having a portion formed on the underlying insulating film and a first overlap portion which overlaps the depression, a second semiconductor portion having a portion formed on the underlying insulating film and a second overlap portion which overlaps the depression, and a third semiconductor portion disposed between the first and second semiconductor portions and having a portion disposed above the depression, wherein overlap width of the first overlap portion and overlap width of the second overlap portion are equal to each other, a gate electrode including a first electrode portion covering upper and side surfaces of the third semiconductor portion and a second electrode portion formed in the depression, and a gate insulating film interposed between the semiconductor structure and the gate electrode.
摘要翻译：公开了一种半导体器件，包括具有凹陷的基底绝缘膜，半导体结构，其包括具有形成在下面的绝缘膜上的部分的第一半导体部分和与凹部重叠的第一重叠部分，第二半导体部分形成有部分在第一半导体部分和第二半导体部分之间并且具有设置在该凹部之上的部分的第三半导体部分，其中第一重叠部分的重叠宽度和第二重叠部分的重叠宽度第二重叠部分彼此相等，栅电极包括覆盖第三半导体部分的上表面和第二表面的第一电极部分和形成在凹陷部中的第二电极部分，以及插入在半导体结构和栅极之间的栅极绝缘膜电极。

17. 发明申请

US20080079057A1 AGING DEVICE 有权
标题翻译：老化设备
公开(公告)号：US20080079057A1
公开(公告)日：2008-04-03
申请号：US11856256
申请日：2007-09-17
申请人： Daisuke Hagishima , Hiroshi Watanabe
发明人： Daisuke Hagishima , Hiroshi Watanabe
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11558 , H01L27/088 , H01L27/115 , H01L27/11521 , H01L29/66825 , H01L29/7881
摘要： An aging device includes a semiconductor substrate, an element isolation insulating layer which is formed in a recessed portion of the semiconductor substrate and which has an upper surface higher than an upper surface of the semiconductor substrate, first and second element regions isolated by the element isolation insulating layer, first and second diffusion layers formed in the semiconductor substrate in the first element region, a first gate insulating film formed on the semiconductor substrate between the first and second diffusion layers, a second gate insulating film formed on the semiconductor substrate in the second element region, and a floating gate electrode formed on the first and second gate insulating films and formed to extend from the first element region to the second element region. The deepest portions of the first and second diffusion layers are isolated from the element isolation insulating layer.
摘要翻译：老化装置包括半导体衬底，元件隔离绝缘层，其形成在半导体衬底的凹陷部分中，并且具有比半导体衬底的上表面高的上表面，通过元件隔离隔离的第一和第二元件区域绝缘层，形成在第一元件区域中的半导体衬底中的第一和第二扩散层，形成在第一和第二扩散层之间的半导体衬底上的第一栅极绝缘膜，形成在第二元件区域中的半导体衬底上的第二栅极绝缘膜元件区域和形成在第一和第二栅极绝缘膜上并形成为从第一元件区域延伸到第二元件区域的浮栅电极。第一和第二扩散层的最深部分与元件隔离绝缘层隔离。

18. 发明授权

US07224019B2 Semiconductor device and method of manufacture thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07224019B2
公开(公告)日：2007-05-29
申请号：US11064453
申请日：2005-02-24
申请人： Katsuhiko Hieda , Daisuke Hagishima
发明人： Katsuhiko Hieda , Daisuke Hagishima
IPC分类号： H01L27/12 , G11C11/34
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L29/42332 , H01L29/7851 , H01L29/7881
摘要： A semiconductor device comprises a semiconductor substrate, an electrically rewritable semiconductor memory cell provided on the semiconductor substrate, the memory cell comprising an island semiconductor portion provided on the surface of the semiconductor substrate or above the semiconductor substrate, a first insulating film provided on a top surface of the island semiconductor portion, a second insulating film provided on a side surface of the island semiconductor portion and being smaller in thickness than the first insulating film, and a charge storage layer provided on the side surface of the island semiconductor portion with the second insulating film interposed therebetween and on a side surface of the first insulating film, a third insulating film provided on the charge storage layer, and a control gate electrode provided on the third insulating film.
摘要翻译：半导体器件包括半导体衬底，设置在半导体衬底上的电可重写半导体存储单元，所述存储单元包括设置在半导体衬底的表面上或半导体衬底上的岛状半导体部分，设置在顶部上的第一绝缘膜岛半导体部分的表面，设置在岛状半导体部分的侧表面上并且厚度小于第一绝缘膜的第二绝缘膜，以及设置在岛半导体部分的侧表面上的电荷存储层，第二绝缘膜具有第二绝缘膜绝缘膜和第一绝缘膜的侧面，设置在电荷存储层上的第三绝缘膜和设置在第三绝缘膜上的控制栅电极。

19. 发明申请

US20070287245A1 Semiconductor device and method of manufacture thereof 失效
公开(公告)号：US20070287245A1
公开(公告)日：2007-12-13
申请号：US11790391
申请日：2007-04-25
申请人： Katsuhiko Hieda , Daisuke Hagishima
发明人： Katsuhiko Hieda , Daisuke Hagishima
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L29/42332 , H01L29/7851 , H01L29/7881
摘要： A semiconductor device comprises a semiconductor substrate, an electrically rewritable semiconductor memory cell provided on the semiconductor substrate, the memory cell comprising an island semiconductor portion provided on the surface of the semiconductor substrate or above the semiconductor substrate, a first insulating film provided on a top surface of the island semiconductor portion, a second insulating film provided on a side surface of the island semiconductor portion and being smaller in thickness than the first insulating film, and a charge storage layer provided on the side surface of the island semiconductor portion with the second insulating film interposed therebetween and on a side surface of the first insulating film, a third insulating film provided on the charge storage layer, and a control gate electrode provided on the third insulating film.

20. 发明申请

US20100250223A1 SEMICONDUCTOR CIRCUIT DETERIORATION SIMULATION METHOD AND COMPUTER PROGRAM MEDIUM 审中-公开
标题翻译：半导体电路测量模拟方法和计算机程序介质
公开(公告)号：US20100250223A1
公开(公告)日：2010-09-30
申请号：US12652434
申请日：2010-01-05
申请人： Daisuke Hagishima , Kazuya Matsuzawa , Yuichiro Mitani , Shigeto Fukatsu , Kouichirou Inoue
发明人： Daisuke Hagishima , Kazuya Matsuzawa , Yuichiro Mitani , Shigeto Fukatsu , Kouichirou Inoue
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A semiconductor circuit deterioration simulation method for a circuit including MOSFETs includes inserting a dynamic voltage source associated with a fluctuation in voltage/current characteristics into each gate terminal of a plurality of MOSFETs in series, calculating dynamic deterioration amounts of the plurality of MOSFETs by performing circuit simulation and calculating a dynamic deterioration amount, and repeating the above processing to perform the circuit deterioration simulation over the long term.
摘要翻译：包括MOSFET的电路的半导体电路劣化模拟方法包括将与电压/电流特性波动相关联的动态电压源串联插入到多个MOSFET的每个栅极端子中，通过执行电路来计算多个MOSFET的动态劣化量模拟并计算动态劣化量，并且重复上述处理以长期执行电路恶化模拟。

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