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11. 发明授权

US08014224B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08014224B2
公开(公告)日：2011-09-06
申请号：US12201024
申请日：2008-08-29
申请人： Kenji Yoshinaga , Fukashi Morishita
发明人： Kenji Yoshinaga , Fukashi Morishita
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： There is provided a semiconductor device supplied with internal power generated by an internal power generation circuit to perform a stable operation and, also, suppress power consumption. A control circuit, a row/column decoder and a sense amplifier are driven by an internal buck voltage. On the other hand, a data path with high power consumption is driven by an external power supply voltage. A level conversion circuit receives an address signal or a command signal having a voltage level of the external power supply voltage, converts the voltage level to the internal buck voltage, and outputs a resultant signal to the control circuit. A level conversion circuit receives a control signal having a voltage level of the internal buck voltage from the control circuit, converts the voltage level to the external power supply voltage, and outputs a resultant signal to the data path.
摘要翻译：提供了由内部发电电路产生的内部电力提供的半导体器件，以执行稳定的操作，并且还抑制功耗。控制电路，行/列解码器和读出放大器由内部降压电压驱动。另一方面，具有高功耗的数据路径由外部电源电压驱动。电平转换电路接收具有外部电源电压的电压电平的地址信号或指令信号，将电压电平转换为内部降压电压，并将结果信号输出到控制电路。电平转换电路从控制电路接收具有内部降压电压的电压电平的控制信号，将电压电平转换为外部电源电压，并将结果信号输出到数据路径。

12. 发明申请

US20110182131A1 SEMICONDUCTOR DEVICE INCLUDING INTERNAL VOLTAGE GENERATION CIRCUIT 失效
标题翻译：包括内部电压发生电路的半导体器件
公开(公告)号：US20110182131A1
公开(公告)日：2011-07-28
申请号：US13080114
申请日：2011-04-05
申请人： Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
发明人： Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
IPC分类号： G11C5/14
CPC分类号： G05F1/468 , G11C5/025 , G11C5/147
摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.
摘要翻译：半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。因此，相对于负电压的变化的响应增加。在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路活性。因此，可以防止待机电流的增加。

13. 发明授权

US07408818B2 Semiconductor device undergoing defect detection test 失效
标题翻译：半导体器件进行缺陷检测测试
公开(公告)号：US07408818B2
公开(公告)日：2008-08-05
申请号：US11703672
申请日：2007-02-08
申请人： Kenji Yoshinaga , Masashi Matsumura , Futoshi Igaue , Mihoko Akiyama , Fukashi Morishita
发明人： Kenji Yoshinaga , Masashi Matsumura , Futoshi Igaue , Mihoko Akiyama , Fukashi Morishita
IPC分类号： G11C11/34
CPC分类号： G11C29/48 , G11C29/12 , G11C29/12005
摘要： A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion supplying a first voltage and a second voltage to the memory portion. The memory portion writes or reads data to or from the memory cells based on the first voltage and the second voltage, and the power supply circuit portion provides a smaller voltage difference between the first voltage and the second voltage in the second operation mode as compared with the voltage difference in the first operation mode.
摘要翻译：半导体器件具有第一操作模式和第二操作模式，其中提供具有比第一操作模式中更高的电压值的电源。半导体器件包括具有用于存储数据的存储单元的存储器部分和向存储器部分提供第一电压和第二电压的电源电路部分。存储器部分基于第一电压和第二电压将数据写入或从存储器单元读取数据，并且电源电路部分在第二操作模式中在第一电压和第二电压之间提供较小的电压差，与第在第一操作模式下的电压差。

14. 发明申请

US20130010513A1 CONTENT ADDRESSABLE MEMORY 有权
公开(公告)号：US20130010513A1
公开(公告)日：2013-01-10
申请号：US13621078
申请日：2012-09-15
申请人： Naoya WATANABE , Isamu Hayashi , Teruhiko Amano , Fukashi Morishita , Kenji Yoshinaga , Mihoko Akiyama , Shinya Miyazaki , Masakazu Ishibashi , Katsumi Dosaka
发明人： Naoya WATANABE , Isamu Hayashi , Teruhiko Amano , Fukashi Morishita , Kenji Yoshinaga , Mihoko Akiyama , Shinya Miyazaki , Masakazu Ishibashi , Katsumi Dosaka
IPC分类号： G11C15/00
CPC分类号： G11C15/043 , G11C7/06 , G11C7/12 , G11C7/14 , G11C7/22 , G11C15/04 , G11C15/046
摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

15. 发明授权

US08164934B2 Content addressable memory 有权
标题翻译：内容可寻址内存
公开(公告)号：US08164934B2
公开(公告)日：2012-04-24
申请号：US12720561
申请日：2010-03-09
申请人： Naoya Watanabe , Isamu Hayashi , Teruhiko Amano , Fukashi Morishita , Kenji Yoshinaga , Mihoko Akiyama , Shinya Miyazaki , Masakazu Ishibashi , Katsumi Dosaka
发明人： Naoya Watanabe , Isamu Hayashi , Teruhiko Amano , Fukashi Morishita , Kenji Yoshinaga , Mihoko Akiyama , Shinya Miyazaki , Masakazu Ishibashi , Katsumi Dosaka
IPC分类号： G11C15/00 , G11C15/04 , G11C7/14 , G11C7/06 , G11C7/12 , G11C7/22
CPC分类号： G11C15/043 , G11C7/06 , G11C7/12 , G11C7/14 , G11C7/22 , G11C15/04 , G11C15/046
摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.
摘要翻译：包括存储数据位的单位单元的多个比特的条目耦合到匹配线。匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流。匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。可以减少内容可寻址存储器的搜索周期中的功耗，并且可以增加搜索操作速度。

16. 发明申请

US20100109761A1 SEMICONDUCTOR DEVICE INCLUDING INTERNAL VOLTAGE GENERATION CIRCUIT 失效
标题翻译：包括内部电压发生电路的半导体器件
公开(公告)号：US20100109761A1
公开(公告)日：2010-05-06
申请号：US12683838
申请日：2010-01-07
申请人： Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
发明人： Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
IPC分类号： G05F1/10
CPC分类号： G05F1/468 , G11C5/025 , G11C5/147
摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.
摘要翻译：半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。因此，相对于负电压的变化的响应增加。在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路活性。因此，可以防止待机电流的增加。

17. 发明申请

US20070216467A1 Semiconductor device including internal voltage generation circuit 有权
标题翻译：半导体器件包括内部电压产生电路
公开(公告)号：US20070216467A1
公开(公告)日：2007-09-20
申请号：US11717717
申请日：2007-03-14
申请人： Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
发明人： Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
IPC分类号： G11C5/14 , H03K17/16
CPC分类号： G05F1/468 , G11C5/025 , G11C5/147
摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.
摘要翻译：半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。因此，相对于负电压的变化的响应增加。在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路活性。因此，可以防止待机电流的增加。

18. 发明申请

US20070183214A1 Semiconductor device undergoing defect detection test 失效
标题翻译：半导体器件进行缺陷检测测试
公开(公告)号：US20070183214A1
公开(公告)日：2007-08-09
申请号：US11703672
申请日：2007-02-08
申请人： Kenji Yoshinaga , Masashi Matsumura , Futoshi Igaue , Mihoko Akiyama , Fukashi Morishita
发明人： Kenji Yoshinaga , Masashi Matsumura , Futoshi Igaue , Mihoko Akiyama , Fukashi Morishita
IPC分类号： G11C29/00 , G11C11/34 , G11C16/04 , G11C7/00 , G11C16/06
CPC分类号： G11C29/48 , G11C29/12 , G11C29/12005
摘要： A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion supplying a first voltage and a second voltage to the memory portion. The memory portion writes or reads data to or from the memory cells based on the first voltage and the second voltage, and the power supply circuit portion provides a smaller voltage difference between the first voltage and the second voltage in the second operation mode as compared with the voltage difference in the first operation mode.
摘要翻译：半导体器件具有第一操作模式和第二操作模式，其中提供具有比第一操作模式中更高的电压值的电源。半导体器件包括具有用于存储数据的存储单元的存储器部分和向存储器部分提供第一电压和第二电压的电源电路部分。存储器部分基于第一电压和第二电压将数据写入或从存储器单元读取数据，并且电源电路部分在第二操作模式中在第一电压和第二电压之间提供较小的电压差，与第在第一操作模式下的电压差。

19. 发明授权

US08154271B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08154271B2
公开(公告)日：2012-04-10
申请号：US13115327
申请日：2011-05-25
申请人： Fukashi Morishita
发明人： Fukashi Morishita
IPC分类号： G05F3/16
CPC分类号： G05F1/465
摘要： The semiconductor integrated circuit device includes load circuits and internal voltage generators for generating internal source voltages for driving the load circuits. Each of the internal voltage generators includes a reference voltage generating circuit for generating reference voltages, and regulator circuits for generating the internal source voltages with reference to the reference voltages. The regulator circuit is formed over an SOI substrate and includes a preamplifier circuit for detecting and amplifying a difference between each of the internal source voltages and each of the reference voltages, a main amplifier circuit for amplifying the output of the preamplifier circuit and generating a control signal, and a driver circuit for generating the internal source voltage in response to the control signal. An input stage of the main amplifier circuit is configured by MOS transistors coupling the gates and bodies of the MOS transistors.
摘要翻译：半导体集成电路装置包括用于产生驱动负载电路的内部源电压的负载电路和内部电压发生器。每个内部电压发生器包括用于产生参考电压的参考电压产生电路和用于参考参考电压产生内部源极电压的调节器电路。调节器电路形成在SOI衬底上，并且包括用于检测和放大每个内部源电压和每个参考电压之间的差的前置放大器电路，用于放大前置放大器电路的输出并产生控制的主放大器电路信号和用于响应于控制信号产生内部源电压的驱动器电路。主放大器电路的输入级由耦合MOS晶体管的栅极和主体的MOS晶体管构成。

20. 发明申请

US20110221419A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20110221419A1
公开(公告)日：2011-09-15
申请号：US13115327
申请日：2011-05-25
申请人： Fukashi Morishita
发明人： Fukashi Morishita
IPC分类号： G05F3/16
CPC分类号： G05F1/465
摘要： The semiconductor integrated circuit device includes load circuits and internal voltage generators for generating internal source voltages for driving the load circuits. Each of the internal voltage generators includes a reference voltage generating circuit for generating reference voltages, and regulator circuits for generating the internal source voltages with reference to the reference voltages. The regulator circuit is formed over an SOI substrate and includes a preamplifier circuit for detecting and amplifying a difference between each of the internal source voltages and each of the reference voltages, a main amplifier circuit for amplifying the output of the preamplifier circuit and generating a control signal, and a driver circuit for generating the internal source voltage in response to the control signal. An input stage of the main amplifier circuit is configured by MOS transistors coupling the gates and bodies of the MOS transistors.
摘要翻译：半导体集成电路装置包括用于产生驱动负载电路的内部源电压的负载电路和内部电压发生器。每个内部电压发生器包括用于产生参考电压的参考电压产生电路和用于参考参考电压产生内部源极电压的调节器电路。调节器电路形成在SOI衬底上，并且包括用于检测和放大每个内部源电压和每个参考电压之间的差的前置放大器电路，用于放大前置放大器电路的输出并产生控制的主放大器电路信号和用于响应于控制信号产生内部源电压的驱动器电路。主放大器电路的输入级由耦合MOS晶体管的栅极和主体的MOS晶体管构成。

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