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11. 发明授权

US5937819A Configuration of operating panel for an engine 失效
标题翻译：配置发动机操作面板
公开(公告)号：US5937819A
公开(公告)日：1999-08-17
申请号：US047472
申请日：1998-03-25
申请人： Hiroyoshi Kouchi , Kazayuki Kobayashi , Shogo Nakamura
发明人： Hiroyoshi Kouchi , Kazayuki Kobayashi , Shogo Nakamura
IPC分类号： F02B63/00 , F02B63/04 , F02B67/00 , F02B75/16 , F02B77/00 , F02B77/13 , F02D11/02 , F02D11/04 , F16B21/04
CPC分类号： F02B75/16 , F02B63/00
摘要： The object of this invention is to provide an operating panel for an engine which would require a smaller number of parts for throttle mechanism, operation panel and the related components. It also requires fewer assembly processes, and improves the outer appearance of the engine. In this operating panel, a cut-off switch to stop the engine is installed in a custom-designed cover, which has a cut-off terminal electrically isolated from a ground, and can electrically ground the cut-off terminal by making a contact with the throttle lever electrically grounded. The operational panel is easily fixed to the fan cover by engaging a protrusion and a hole. The operational panel has a groove to run a fuel pipe.
摘要翻译：本发明的目的是提供一种用于发动机的操作面板，其需要较少数量的用于节流机构，操作面板和相关部件的部件。它还需要更少的装配过程，并且改善发动机的外观。在这个操作面板上，用于停止发动机的切断开关安装在定制设计的盖子中，该盖子具有与地面电隔离的截止端子，并且可以通过与截止端子油门杆电接地。操作板通过接合突起和孔容易地固定到风扇盖。操作面板具有用于运行燃料管的凹槽。

12. 发明授权

US09315289B2 Packaging member and packaging method 有权
标题翻译：包装成分和包装方法
公开(公告)号：US09315289B2
公开(公告)日：2016-04-19
申请号：US13313155
申请日：2011-12-07
申请人： Shogo Nakamura , Tomokazu Saito , Atsushi Inoue , Seiji Terazawa , Mizuho Imaruoka , Chiharu Matsui
发明人： Shogo Nakamura , Tomokazu Saito , Atsushi Inoue , Seiji Terazawa , Mizuho Imaruoka , Chiharu Matsui
IPC分类号： B65D5/50
CPC分类号： B65D5/5004 , B65D5/505 , B65D5/5054 , B65D2585/689 , G03G2215/0875 , G03G2215/0886
摘要： A packaging member includes a cushioning member that holds a holding part of a to-be-packaged member different from a predetermined part of the to-be-packaged member without coming into contact with the predetermined part of the to-be-packaged member. The cushioning member cushions a shock transmitting to the to-be-packaged member, and the packaging member packages the to-be-packaged member via the cushioning member.
摘要翻译：包装部件包括缓冲部件，该缓冲部件与未被包装部件的预定部分接触而保持与被包装部件的预定部分不同的被包装部件的保持部。缓冲构件缓冲向被包装构件传递的冲击，并且包装构件经由缓冲构件包装待包装构件。

13. 发明申请

US20090015451A1 FLASH A/D CONVERTER 失效
标题翻译：闪存A / D转换器
公开(公告)号：US20090015451A1
公开(公告)日：2009-01-15
申请号：US12140803
申请日：2008-06-17
申请人： Junji Toyomura , Yukitoshi Yamashita , Shogo Nakamura , Norifumi Kanagawa , Yasuhide Shimizu , Koichi Ono
发明人： Junji Toyomura , Yukitoshi Yamashita , Shogo Nakamura , Norifumi Kanagawa , Yasuhide Shimizu , Koichi Ono
IPC分类号： H03M1/12 , H03M1/34
CPC分类号： H03M1/0863 , H03F3/45188 , H03F2203/45302 , H03F2203/45396 , H03M1/205 , H03M1/365
摘要： A flash A/D converter includes a reference voltage generator for generating a plurality of reference voltages, a first group of amplifiers having a plurality of amplifiers each of which amplifies a difference voltage between each reference voltage generated by the reference voltage generator and a voltage of an input signal, and a second group of amplifiers having a plurality of amplifiers. Each amplifier of the first group of amplifiers is a differential amplifier having a differential pair formed of a plurality of sets of cascode-connected transistors, and has a first switch for short-circuiting respective cascode connection portions of the plurality of transistors configuring the differential pair. Each amplifier of the second group of amplifiers is a differential amplifier having a differential pair formed of at least two transistors and has a second switch for short-circuiting a portion between input units of the differential pair. The first switch and the second switch are controlled to open and close by a control clock of a predetermined period.
摘要翻译：闪光A / D转换器包括用于产生多个参考电压的参考电压发生器，具有多个放大器的第一组放大器，每个放大器放大由参考电压发生器产生的每个参考电压之间的差值电压和输入信号和具有多个放大器的第二组放大器。第一组放大器的每个放大器是具有由多组共源共栅连接的晶体管形成的差分对的差分放大器，并且具有第一开关，用于短路构成差分对的多个晶体管的各自的共源共栅连接部分。第二组放大器的每个放大器是具有由至少两个晶体管形成的差分对的差分放大器，并且具有用于使差分对的输入单元之间的部分短路的第二开关。第一开关和第二开关通过预定周期的控制时钟被控制为打开和关闭。

14. 发明授权

US07649486B2 Flash A/D converter 失效
标题翻译：闪存A / D转换器
公开(公告)号：US07649486B2
公开(公告)日：2010-01-19
申请号：US12140803
申请日：2008-06-17
申请人： Junji Toyomura , Yukitoshi Yamashita , Shogo Nakamura , Norifumi Kanagawa , Yasuhide Shimizu , Koichi Ono
发明人： Junji Toyomura , Yukitoshi Yamashita , Shogo Nakamura , Norifumi Kanagawa , Yasuhide Shimizu , Koichi Ono
IPC分类号： H03M1/36
CPC分类号： H03M1/0863 , H03F3/45188 , H03F2203/45302 , H03F2203/45396 , H03M1/205 , H03M1/365
摘要： A flash A/D converter includes a reference voltage generator for generating a plurality of reference voltages, a first group of amplifiers having a plurality of amplifiers each of which amplifies a difference voltage between each reference voltage generated by the reference voltage generator and a voltage of an input signal, and a second group of amplifiers having a plurality of amplifiers. Each amplifier of the first group of amplifiers is a differential amplifier having a different pair formed of a plurality of sets of cascade-connected transistors, and has a first switch for short-circuiting respective cascade connection portions of the plurality of transistors configuring the differential pair. Each amplifier of the second group of amplifiers is a differential amplifier having a differential pair formed of at least two transistors and has a second switch for short-circuiting a portion between input units of the differential pair. The first switch and the second switch are controlled to open and close by a control clock of a predetermined period.
摘要翻译：闪光A / D转换器包括用于产生多个参考电压的参考电压发生器，具有多个放大器的第一组放大器，每个放大器放大由参考电压发生器产生的每个参考电压之间的差值电压和输入信号和具有多个放大器的第二组放大器。第一组放大器的每个放大器是具有由多组级联晶体管组成的不同对的差分放大器，并且具有第一开关，用于短路构成差分对的多个晶体管的相应级联连接部分。第二组放大器的每个放大器是具有由至少两个晶体管形成的差分对的差分放大器，并且具有用于使差分对的输入单元之间的部分短路的第二开关。第一开关和第二开关通过预定周期的控制时钟被控制为打开和关闭。

15. 发明申请

US20110001648A1 FOLDING CIRCUIT AND ANALOG-TO-DIGITAL CONVERTER 失效
标题翻译：折叠电路和模拟数字转换器
公开(公告)号：US20110001648A1
公开(公告)日：2011-01-06
申请号：US12439757
申请日：2007-09-04
申请人： Takeshi Ohkawa , Koichi Ono , Kouji Matsuura , Yukitosi Yamasita , Junji Toyomura , Shogo Nakamura , Norifimi Kanagawa
发明人： Takeshi Ohkawa , Koichi Ono , Kouji Matsuura , Yukitosi Yamasita , Junji Toyomura , Shogo Nakamura , Norifimi Kanagawa
IPC分类号： H03M1/12 , H03F3/68
CPC分类号： H03M1/0863 , H03M1/0682 , H03M1/141 , H03M1/205 , H03M1/365
摘要： A folding circuit and an analog-to-digital converter wherein a response to small signals is improved, a load on a clock signal can be reduced, and the increase of circuit area can be prevented. The circuit includes a reference voltage generating circuit that generates a plurality of differential voltages as reference voltages, and a plurality of amplification circuits that convert differential voltages between the plurality of reference voltages and an analog input voltage to differential currents, and output these differential currents. The output ends of the amplification circuits are alternately connected. Each of the amplification circuit is configured by a differential amplifier circuit having cascode output transistors (145, 146). A switch (144), which is turned on in synchronization with the control clock, is provided between the both sources of the cascode output transistors (145,146).
摘要翻译：折叠电路和模数转换器，其中对小信号的响应得到改善，可以减少对时钟信号的负担，并且可以防止电路面积的增加。该电路包括产生多个差分电压作为参考电压的参考电压产生电路和将多个参考电压之间的差分电压与模拟输入电压转换成差分电流的多个放大电路，并输出这些差分电流。放大电路的输出端交替连接。每个放大电路由具有共源共栅输出晶体管（145,146）的差分放大器电路构成。在共源共栅输出晶体管（145,146）的两个源之间提供与控制时钟同步导通的开关（144）。

16. 发明授权

US4932063A Noise suppression apparatus 失效
标题翻译：噪声抑制装置
公开(公告)号：US4932063A
公开(公告)日：1990-06-05
申请号：US265407
申请日：1988-10-31
申请人： Shogo Nakamura
发明人： Shogo Nakamura
IPC分类号： G10L15/20 , G10L21/02
CPC分类号： G10L21/0208 , G10L2021/02165
摘要： A noise suppression apparatus has a main microphone for mainly picking up a voice and for outputting an input signal including an audio signal and a first noise component generated from a noise source, a reference microphone for picking up a second noise component generated from the noise source, a filter bank for band-dividing the input signal from the main microphone and the second noise component from the reference microphone, and a noise cancel circuit for obtaining a phase difference between the input signal and the second noise component with respect to each divided band of the filter bank so as to correct the input signal based on the phase difference and for cancelling the first noise component in the input signal by use of the corrected input signal.
摘要翻译：噪声抑制装置具有用于主要拾取语音并用于输出包括从噪声源产生的音频信号和第一噪声分量的输入信号的主麦克风，用于拾取从噪声源产生的第二噪声分量的参考麦克风，用于对来自主麦克风的输入信号进行频谱分割的滤波器组和来自参考麦克风的第二噪声分量;以及噪声消除电路，用于相对于每个分频带获得输入信号和第二噪声分量之间的相位差以便基于相位差来校正输入信号，并且通过使用校正的输入信号来消除输入信号中的第一噪声分量。

17. 发明授权

US4833717A Voice spectrum analyzing system and method 失效
标题翻译：语音频谱分析系统及方法
公开(公告)号：US4833717A
公开(公告)日：1989-05-23
申请号：US932602
申请日：1986-11-20
申请人： Shogo Nakamura , Tomofumi Nakatani
发明人： Shogo Nakamura , Tomofumi Nakatani
IPC分类号： G10L11/00 , G10L15/02
CPC分类号： G10L15/02
摘要： A voice spectrum analyzing method and system subjects a voice signal to frequency analysis by passing the voice signal through a filter bank containing a plurality of band pass filters each having a different band pass filter range to produce a voice spectral pattern over a predetermined frequency range. The voice spectral pattern is sampled at a predetermined sampling time interval successively, and each of the sampled voice spectral patterns is stored for a predetermined time period. While the voice spectral pattern is retained, it is scanned once in a predetermined time sequence, thereby forming an approximate periodic signal from a series of the scanned voice spectral voice patterns. And the periodic signal thus formed is then digitized and filtered through a digital high pass filter, thereby obtaining a high frequency component from the periodic signal which indicates a feature parameter of the voice signal.
摘要翻译：语音频谱分析方法和系统通过使语音信号通过包含多个带通滤波器范围的多个带通滤波器的滤波器组来对语音信号进行频率分析，以在预定频率范围内产生语音频谱图案。语音频谱模式以预定的采样时间间隔连续采样，并且每个采样的声频谱图案被存储预定的时间段。当声音谱图被保留时，以预定的时间顺序扫描一次，从而形成来自一系列扫描的声音频谱语音模式的近似周期信号。然后由此形成的周期信号通过数字高通滤波器进行数字化和滤波，从而从表示语音信号的特征参数的周期信号中获得高频分量。

18. 发明授权

US10513408B2 Sheet conveying device and image forming apparatus incorporating the sheet conveying device 有权
公开(公告)号：US10513408B2
公开(公告)日：2019-12-24
申请号：US16001009
申请日：2018-06-06
申请人： Shogo Nakamura , Takehiro Fujita , Tomoki Shimohira
发明人： Shogo Nakamura , Takehiro Fujita , Tomoki Shimohira
IPC分类号： B65H9/00 , B65H7/14 , B65H5/06 , B65H7/08 , B65H7/10 , B65H9/20
摘要： A sheet conveying device, which is included in an image forming apparatus, includes a pair of rollers configured to convey a sheet in a sheet conveyance passage, a detector configured to optically detect an attitude of the sheet, one of a rotation device to rotate the pair of rollers in a direction parallel to a plane of the sheet and a moving device to move the pair of rollers in a width direction, and a controller configured to correct the attitude of the pair of rollers at a time interval, based on a detection result obtained by the detector. The controller performs the correcting operation by setting, according to reflectance of the sheet, at least one of a light emission time of the detector, the time interval of the correcting operation, light emission intensity of the detector and a conveying speed of the sheet.

19. 发明授权

US4958311A Composite finite impulse response digital filter 失效
标题翻译：复合有限脉冲响应数字滤波器
公开(公告)号：US4958311A
公开(公告)日：1990-09-18
申请号：US328970
申请日：1989-03-27
申请人： Yukio Kadowaki , Shigeki Matsuoka , Shogo Nakamura
发明人： Yukio Kadowaki , Shigeki Matsuoka , Shogo Nakamura
IPC分类号： H03H17/00 , H03H17/06
CPC分类号： H03H17/06
摘要： A composite finite impulse response digital filter for use in an image processing apparatus or the like includes a plurality of sub-filters connected in series. In each sub-filter, a random access memory (RAM) is provided for storing an input data and a barrel shifter is provided for shifting the data to a least significant bit (LSB) or most significant bit (MSB) side over the number of shifts corresponding to a first control signal. Because of the provision of the barrel shifter in each sub-circuit, it is not necessary to shift a data input into an input terminal over a predetermined number of bits before storing into the RAM. Thus, the memory capacity of the RAM can be significantly reduced in size.
摘要翻译：用于图像处理装置等的复合有限脉冲响应数字滤波器包括串联连接的多个子滤波器。在每个子滤波器中，提供了用于存储输入数据的随机存取存储器（RAM），并且提供桶形移位器用于将数据移位到最低有效位（LSB）或最高有效位（MSB）侧的数量对应于第一控制信号的位移。由于在每个子电路中提供桶形移位器，因此在存储到RAM之前不需要将预定数量的位的数据输入移入输入端。因此，RAM的存储器容量可以大大减小。

20. 发明授权

US4634966A Binary processing of sound spectrum 失效
标题翻译：声谱的二进制处理
公开(公告)号：US4634966A
公开(公告)日：1987-01-06
申请号：US713431
申请日：1985-03-19
申请人： Tomofumi Nakatani , Shogo Nakamura
发明人： Tomofumi Nakatani , Shogo Nakamura
IPC分类号： G10L15/02 , G01H3/08 , G01R23/16 , G10L11/00
CPC分类号： G01R23/16 , G01H3/08
摘要： A frequency spectral distribution of sound signal has a plurality of discrete data at respective channels where sampling takes place. Such a spectral distribution, defining a parallel signal, is converted into a time series signal which is used to produce a peak-detected signal and a zero-cross signal. Then, based on the timing of the zero-cross signal, the peak-detected signal is compared with the original parallel signal to process the original parallel signal to be binary-valued. The present invention provides a simple hardware structure having the above-described function.
摘要翻译：声音信号的频谱分布在进行采样的各个信道上具有多个离散数据。定义并行信号的这种频谱分布被转换为用于产生峰值检测信号和零交叉信号的时间序列信号。然后，基于零交叉信号的定时，将峰值检测信号与原始并行信号进行比较，以处理原始并行信号为二值。本发明提供具有上述功能的简单的硬件结构。

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