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11. 发明授权

US06818523B2 Semiconductor storage device manufacturing method which forms a hydrogen diffusion inhibiting layer 失效
标题翻译：形成氢扩散抑制层的半导体存储装置的制造方法
公开(公告)号：US06818523B2
公开(公告)日：2004-11-16
申请号：US10602644
申请日：2003-06-25
申请人： Hiroshi Miki , Keiko Kushida , Yasuhiro Shimamoto , Shinichiro Takatani , Yoshihisa Fujisaki , Hiromi Nakai
发明人： Hiroshi Miki , Keiko Kushida , Yasuhiro Shimamoto , Shinichiro Takatani , Yoshihisa Fujisaki , Hiromi Nakai
IPC分类号： Y01L2120
CPC分类号： H01L28/75 , H01L28/55 , H01L28/57 , H01L28/60
摘要： A method for forming a semiconductor storage device includes steps of forming a memory cell transistor, forming a first plug connected to the memory cell transistor, forming a second plug of a hydrogen diffusion inhibiting layer, forming capacitor electrodes and a capacitor insulator between the capacitor electrodes and forming a hydrogen adsorption inhibiting layer.
摘要翻译：一种形成半导体存储装置的方法，包括：形成存储单元晶体管，形成连接到存储单元晶体管的第一插头，形成氢扩散抑制层的第二插头，在电容器电极之间形成电容器电极和电容器绝缘体并形成氢吸附抑制层。

12. 发明授权

US07256437B2 Semiconductor storage device which includes a hydrogen diffusion inhibiting layer 失效
标题翻译：包括氢扩散抑制层的半导体存储装置
公开(公告)号：US07256437B2
公开(公告)日：2007-08-14
申请号：US10920344
申请日：2004-08-18
申请人： Hiroshi Miki , Keiko Kushida , Yasuhiro Shimamoto , Shinichiro Takatani , Yoshihisa Fujisaki , Hiromi Nakai
发明人： Hiroshi Miki , Keiko Kushida , Yasuhiro Shimamoto , Shinichiro Takatani , Yoshihisa Fujisaki , Hiromi Nakai
IPC分类号： H01L29/76
CPC分类号： H01L28/75 , H01L28/55 , H01L28/57 , H01L28/60
摘要： The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively acts as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.
摘要翻译：电容器的上电极由层叠膜构成，其用于防止氢原子到达电容器电极并降低性能。在一个示例中，四层上电极分别用作肖特基势垒层，氢扩散防止层，反应防止层和吸附抑制层。因此，可以防止由于还原气氛导致半导体器件中的电容下降，绝缘不良和电极剥离的发生。另外，可以提高装置的长期可靠性。

13. 发明申请

US20050051821A1 Semiconductor storage device which includes a hydrogen diffusion inhibiting layer 失效
标题翻译：包括氢扩散抑制层的半导体存储装置
公开(公告)号：US20050051821A1
公开(公告)日：2005-03-10
申请号：US10920344
申请日：2004-08-18
申请人： Hiroshi Miki , Keiko Kushida , Yasuhiro Shimamoto , Shinichiro Takatani , Yoshihisa Fujisaki , Hiromi Nakai
发明人： Hiroshi Miki , Keiko Kushida , Yasuhiro Shimamoto , Shinichiro Takatani , Yoshihisa Fujisaki , Hiromi Nakai
IPC分类号： H01L21/02 , H01L29/76
CPC分类号： H01L28/75 , H01L28/55 , H01L28/57 , H01L28/60
摘要： The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively acts as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.
摘要翻译：电容器的上电极由层叠膜构成，其用于防止氢原子到达电容器电极并降低性能。在一个示例中，四层上电极分别用作肖特基势垒层，氢扩散防止层，反应防止层和吸附抑制层。因此，可以防止由于还原气氛导致半导体器件中的电容下降，绝缘不良和电极剥离的发生。另外，可以提高装置的长期可靠性。

14. 发明授权

US06822276B1 Memory structure with a ferroelectric capacitor 失效
标题翻译：具有铁电电容的存储器结构
公开(公告)号：US06822276B1
公开(公告)日：2004-11-23
申请号：US09391250
申请日：1999-09-07
申请人： Kazuyoshi Torii , Hiroshi Miki , Yoshihisa Fujisaki
发明人： Kazuyoshi Torii , Hiroshi Miki , Yoshihisa Fujisaki
IPC分类号： H01L27108
CPC分类号： H01L28/56 , H01L21/28568 , H01L27/10852 , H01L27/10855 , H01L28/55 , H01L28/75
摘要： It is an object of the present invention to provide a fine memory cell structure preventing a reaction between an interlayer insulating film and a ferroelectric film and suitable for high integration. According to the invention, there is provided a structure in which a reaction barrier film 43 is interposed between a ferroelectric film 71 and an interlayer insulating film 32 and side walls of a diffusion barrier film 51 are not brought into direct contact with the ferroelectric film 71. Thereby, the reaction between the interlayer insulating film 32 and the ferroelectric film 71 can be restrained and exfoliation of the ferroelectric film 71 can be prevented.
摘要翻译：本发明的目的是提供一种防止层间绝缘膜和铁电体膜之间的反应并且适合于高集成度的精细存储单元结构。根据本发明，提供一种结构，其中反应阻挡膜43介于铁电膜71和层间绝缘膜32之间，并且扩散阻挡膜51的侧壁不与铁电体膜71直接接触由此，能够抑制层间绝缘膜32与强电介质膜71的反应，能够防止铁电体膜71的剥离。

15. 发明申请

US20050074936A1 Method of fabricating a semiconductor device including a reaction barrier film, a diffusion barrier film and a ferroelectric film 审中-公开
标题翻译：制造包括反应阻挡膜，扩散阻挡膜和铁电体膜的半导体器件的方法
公开(公告)号：US20050074936A1
公开(公告)日：2005-04-07
申请号：US10968077
申请日：2004-10-20
申请人： Kazuyoshi Torii , Hiroshi Miki , Yoshihisa Fujisaki
发明人： Kazuyoshi Torii , Hiroshi Miki , Yoshihisa Fujisaki
IPC分类号： H01L27/10 , H01L21/02 , H01L21/285 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108 , H01L21/00
CPC分类号： H01L28/56 , H01L21/28568 , H01L27/10852 , H01L27/10855 , H01L28/55 , H01L28/75
摘要： A method of fabricating a semiconductor device, is provided including forming an insulating film having an opening portion on a substrate having a transistor, filling a conductive film in the opening portion, forming a reaction barrier film functioning to prevent a reaction on the insulating film, and forming a diffusion barrier film on the conductive film. Next a first electrode is formed on the diffusion barrier film, a ferroelectric film, including at least one element of the group consisting of lead, barium and bismuth is formed on the first electrode after the step of forming the reaction barrier film, and a second electrode is formed on the ferroelectric film.
摘要翻译：提供一种制造半导体器件的方法，包括：在具有晶体管的衬底上形成具有开口部分的绝缘膜，在开口部分填充导电膜，形成用于防止对绝缘膜发生反应的反应阻挡膜，并在导电膜上形成扩散阻挡膜。接下来，在扩散阻挡膜上形成第一电极，在形成反应阻挡膜的步骤之后，在第一电极上形成包括由铅，钡和铋组成的组中的至少一种元素的铁电体膜，第二电极形成第二电极电极形成在铁电体膜上。

16. 发明授权

US06309894B1 Semiconductor memory and method of manufacturing the same 失效
标题翻译：半导体存储器及其制造方法
公开(公告)号：US06309894B1
公开(公告)日：2001-10-30
申请号：US09214382
申请日：1999-01-06
申请人： Hiroshi Miki , Keiko Abdelghafar , Yoshihisa Fujisaki
发明人： Hiroshi Miki , Keiko Abdelghafar , Yoshihisa Fujisaki
IPC分类号： H01G706
CPC分类号： H01L28/56 , H01L21/02197 , H01L21/02323 , H01L21/0234 , H01L28/75
摘要： A semiconductor memory which is improved in reliability by preventing the lowering of capacitance and defective insulation, especially, electrode delamination caused by the formation of the passivation film (insulating film) of a capacitor using a high-dielectric-constant or ferroelectric material by plasma processing at a relatively low temperature and a method for manufacturing the memory. The semiconductor memory has an integrated capacitor composed of a capacitor structure constituted of an upper electrode, a lower electrode, and a capacitor insulating film (of a high-dielectric-constant or ferroelectric thin film) which is held between electrodes and serves as a capacitor insulating film and a protective insulating film which covers the capacitor structure and is formed by plasma treatment. An oxygen introducing layer is further formed on the surface of the thin film constituting the capacitor insulating film. In the manufacturing process of the memory, for example, the oxygen introducing layer is formed on the surface of the high-dielectric-constant or ferroelectric material by introducing oxygen to the boundary between the electrode and the material by conducting heat treatment in an oxygen atmosphere before the protective insulating film (SiO2 passivation film) is formed by plasma treatment after the formation of the electrode. Therefore, lowering of capacitance, defective insulation, and especially, electrode delamination, which are caused by the formation of the passivation film (insulating film), can be prevented.
摘要翻译：一种半导体存储器，其通过防止电容降低和绝缘不良，特别是由于通过等离子体处理使用高介电常数或铁电材料的电容器的钝化膜（绝缘膜）形成而导致的电极分层而提高了可靠性在相对低的温度下和用于制造存储器的方法。半导体存储器具有由电容器结构构成的集成电容器，该电容器结构由保持在电极之间的上电极，下电极和电容器绝缘膜（高介电常数或铁电薄膜）构成，并用作电容器绝缘膜和覆盖电容器结构并通过等离子体处理形成的保护绝缘膜。在构成电容器绝缘膜的薄膜的表面上还形成氧气引入层。在记忆体的制造过程中，例如，通过在氧气氛中进行热处理，将氧引入电极与材料之间的边界，在高介电常数或铁电体材料的表面上形成氧气导入层之前，在形成电极之后，通过等离子体处理形成保护绝缘膜（SiO 2钝化膜）。因此，可以防止由形成钝化膜（绝缘膜）引起的电容降低，绝缘性差，特别是电极分层。

17. 发明授权

US06632721B1 Method of manufacturing semiconductor devices having capacitors with electrode including hemispherical grains 失效
标题翻译：制造具有包括半球形晶粒的电极的电容器的半导体器件的方法
公开(公告)号：US06632721B1
公开(公告)日：2003-10-14
申请号：US09602887
申请日：2000-06-23
申请人： Shinpei Iijima , Satoshi Yamamoto , Jun Kuroda , Hiroshi Miki , Yoshihisa Fujisaki , Tadanori Yoshida , Kenichi Yamaguchi
发明人： Shinpei Iijima , Satoshi Yamamoto , Jun Kuroda , Hiroshi Miki , Yoshihisa Fujisaki , Tadanori Yoshida , Kenichi Yamaguchi
IPC分类号： H01L2120
CPC分类号： H01L28/84 , H01L27/10814 , H01L27/10894
摘要： In a method of manufacturing a semiconductor integrated circuit device in which a lower electrode of a capacitor is composed of a polycrystalline silicon film having a surface area increased by surface roughening, an impurity is introduced into the polycrystalline silicon film by vapor phase diffusion in order to reduce the resistance of the lower electrode.
摘要翻译：在制造半导体集成电路器件的方法中，其中电容器的下电极由具有由表面粗糙度增加的表面积的多晶硅膜构成，通过气相扩散将杂质引入到多晶硅膜中，以便降低下电极的电阻

18. 发明授权

US06420192B2 Method of manufacturing semiconductor memory 失效
标题翻译：制造半导体存储器的方法
公开(公告)号：US06420192B2
公开(公告)日：2002-07-16
申请号：US09968921
申请日：2001-10-03
申请人： Hiroshi Miki , Keiko Abdelghafar , Yoshihisa Fujisaki
发明人： Hiroshi Miki , Keiko Abdelghafar , Yoshihisa Fujisaki
IPC分类号： H01G706
CPC分类号： H01L28/56 , H01L21/02197 , H01L21/02323 , H01L21/0234 , H01L28/75
摘要： A semiconductor memory which is improved in reliability by preventing the lowering of capacitance and defective insulation, especially, electrode delamination. The semiconductor memory has an integrated capacitor composed of a capacitor structure constituted of an upper electrode, a lower electrode, and a capacitor insulating film (of a high-dielectric-constant or ferroelectric thin film) which is held between electrodes and serves as a capacitor insulating film, and a protective insulating film which covers the capacitor structure and is formed by plasma treatment after electrode formation. An oxygen introducing layer is formed on the surface of the capacitor insulating film. The oxygen introducing layer can be formed on the surface of the high-dielectric-constant or ferroelectric material by introducing oxygen to the boundary between the electrode and the material by conducting heat treatment in an oxygen atmosphere before the protective insulating film (SiO2 passivation film) is formed.
摘要翻译：一种半导体存储器，其通过防止电容降低和绝缘不良，特别是电极分层而提高了可靠性。半导体存储器具有由电容器结构构成的集成电容器，该电容器结构由保持在电极之间的上电极，下电极和电容器绝缘膜（高介电常数或铁电薄膜）构成，并用作电容器绝缘膜和覆盖电容器结构的保护绝缘膜，并且在电极形成之后通过等离子体处理形成。在电容器绝缘膜的表面上形成氧气引入层。通过在保护绝缘膜（SiO 2钝化膜）之前通过在氧气氛中进行热处理将氧引入电极和材料之间的边界，可以在高介电常数或铁电材料的表面上形成氧气引入层，形成了。

19. 发明授权

US06509246B2 Production of semiconductor integrated circuit 失效
公开(公告)号：US06509246B2
公开(公告)日：2003-01-21
申请号：US09877207
申请日：2001-06-11
申请人： Hiroshi Miki , Yasuhiro Shimamoto , Masahiko Hiratani , Tomoyuki Hamada
发明人： Hiroshi Miki , Yasuhiro Shimamoto , Masahiko Hiratani , Tomoyuki Hamada
IPC分类号： H01L2120
CPC分类号： H01L28/84 , H01L27/10814 , H01L28/91
摘要： A semiconductor integrated circuit in which the storage capacitor has an increased capacitance and a decreased leakage current. The storage capacitor is formed by the steps of: forming a polysilicon bottom electrode having semispherical silicon crystals formed thereon; performing plasma nitriding on the surface of said bottom electrode at a temperature lower than 550° C., thereby forming a film of silicon nitride having a film thickness smaller than 1.5 nm; and depositing a film of amorphous tantalum pentoxide and then crystallizing said amorphous tantalum pentoxide. The silicon nitride film has improved resistance to oxidation and also has a reduced leakage current. As a result, the polysilicon bottom electrode becomes resistant to oxidation and the storage capacitor increases in capacitance and decreases in leakage current.

20. 发明授权

US07709315B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07709315B2
公开(公告)日：2010-05-04
申请号：US11773842
申请日：2007-07-05
申请人： Naoki Tega , Hiroshi Miki , Yasuhiro Shimamoto , Digh Hisamoto , Tetsuya Ishimaru
发明人： Naoki Tega , Hiroshi Miki , Yasuhiro Shimamoto , Digh Hisamoto , Tetsuya Ishimaru
IPC分类号： H01L21/8238
CPC分类号： H01L29/792 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L27/11573 , H01L29/42324 , H01L29/4234 , H01L29/42344 , H01L29/66833
摘要： An interface between a bottom oxide film and a silicon nitride film in a neighborhood of a bottom part of a select gate is located at a position as high as or higher than that of an interface between a silicon substrate (p-type well) and a gate insulating film (d≧0) Further, the gate insulating film and the bottom oxide film are successively and smoothly jointed in the neighborhood of the bottom part of the select gate. By this configuration, localization in a distribution of electrons injected into the silicon nitride film in the writing is mitigated and electrons to be left unerased by hot-hole erasing are reduced. Therefore, not only the increase ratio of the electrons left unerased in the writing can be reduced, but also the problem in which the threshold voltage does not decrease to the predetermined voltage in the deletion can be suppressed.
摘要翻译：在选择栅极的底部附近的底部氧化物膜和氮化硅膜之间的界面位于硅衬底（p型阱）和硅衬底（p型阱）之间的界面的高度或更高的位置栅极绝缘膜（d≥0）此外，栅极绝缘膜和底部氧化物膜在选择栅极的底部附近依次平滑地接合。通过这种配置，减轻了在写入中注入到氮化硅膜中的电子分布中的定位，并且减少了通过热孔擦除而未被消除的电子。因此，不仅可以减少在写入时未加电的电子的增加比例，还可以抑制在删除中阈值电压不降低到预定电压的问题。

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