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11. 发明授权

US08139332B2 Level conversion circuit and semiconductor integrated circuit device employing the level conversion circuit 有权
标题翻译：电平转换电路和采用电平转换电路的半导体集成电路器件
公开(公告)号：US08139332B2
公开(公告)日：2012-03-20
申请号：US13095480
申请日：2011-04-27
申请人： Kazuo Tanaka , Hiroyuki Mizuno , Rie Nishiyama , Manabu Miyamoto
发明人： Kazuo Tanaka , Hiroyuki Mizuno , Rie Nishiyama , Manabu Miyamoto
IPC分类号： H02H3/20 , H01L23/60
CPC分类号： H03K3/356113 , H01L2924/0002 , H03K3/356104 , H01L2924/00
摘要： In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.
摘要翻译：在安装在使用多个高压和低压电源的集成电路装置中的电平转换电路中，提供到差分输入的输入。在降压电路中，栅极和漏极之间以及栅极和源极之间未提供3.3 V的MOS晶体管使用薄的氧化物层。在升高电路中，提供逻辑运算功能。

12. 发明申请

US20110271066A1 STORAGE SYSTEM AND DATA MANAGEMENT METHOD 有权
标题翻译：存储系统和数据管理方法
公开(公告)号：US20110271066A1
公开(公告)日：2011-11-03
申请号：US13179403
申请日：2011-07-08
申请人： Tatsuya NINOMIYA , Kazuo Tanaka
发明人： Tatsuya NINOMIYA , Kazuo Tanaka
IPC分类号： G06F12/00
CPC分类号： G06F12/0868 , G06F12/0811 , G06F2212/284
摘要： The present invention comprises a CHA 110 which transmits/receives data to/from an external device, a DKA 140 which transmits/receives data to/from an HDD unit 200, a primary cache unit 120 which has a primary cache memory 124, a secondary cache unit 130 which is installed between the primary cache unit 120 and the DKA 140 and has a secondary cache memory 134, a CCP 121 which stores write target data received by the CHA 110 in the primary cache memory 124, and a CCP 131 which stores the write target data in the secondary cache memory 134, and transfers the write target data stored in the secondary cache memory 134 to the DKA 140.
摘要翻译：本发明包括向外部设备发送/接收数据的CHA 110，从HDD单元200发送/接收数据的DKA140，具有主高速缓存存储器124的主高速缓存单元120，辅助缓存单元120 高速缓存单元130安装在主缓存单元120和DKA 140之间，并且具有二级高速缓存存储器134，存储由CHA 110接收的写目标数据在一级高速缓冲存储器124中的CCP 121和存储在二次高速缓存存储器134中的写入目标数据，并将存储在二次高速缓冲存储器134中的写入目标数据传送到DKA 140。

13. 发明授权

US08013656B2 Semicondutor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08013656B2
公开(公告)日：2011-09-06
申请号：US12944898
申请日：2010-11-12
申请人： Yusuko Kanno , Kazuo Tanaka , Shunsuke Toyoshima , Takeo Toba
发明人： Yusuko Kanno , Kazuo Tanaka , Shunsuke Toyoshima , Takeo Toba
IPC分类号： H03L5/00
CPC分类号： H03K19/018521 , H01L27/0928 , H01L27/105 , H03K3/356113
摘要： A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.
摘要翻译：提供了包括能够以低成本进行低电压高速运行的I / O电路的半导体集成电路装置。在I / O电路中，当I / O电压（例如3.3V）降低到预定电压（例如1.8V）时，导致速度劣化的部分是电平转换单元和预缓冲单元用于驱动主要大型缓冲区。鉴于此，高电压被施加到电平转换器和预缓冲器电路。通过这样做，可以以低成本实现能够进行低电压高速操作的I / O电路。

14. 发明授权

US07944656B2 Level conversion circuit and semiconductor integrated circuit device employing the level conversion circuit 有权
标题翻译：电平转换电路和采用电平转换电路的半导体集成电路器件
公开(公告)号：US07944656B2
公开(公告)日：2011-05-17
申请号：US12169408
申请日：2008-07-08
申请人： Kazuo Tanaka , Hiroyuki Mizuno , Rie Nishiyama , Manabu Miyamoto
发明人： Kazuo Tanaka , Hiroyuki Mizuno , Rie Nishiyama , Manabu Miyamoto
IPC分类号： H02H3/20 , H01L23/60
CPC分类号： H03K3/356113 , H01L2924/0002 , H03K3/356104 , H01L2924/00
摘要： In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.
摘要翻译：在安装在使用多个高压和低压电源的集成电路装置中的电平转换电路中，提供到差分输入的输入。在降压电路中，栅极和漏极之间以及栅极和源极之间未提供3.3 V的MOS晶体管使用薄的氧化物层。在升高电路中，提供逻辑运算功能。

15. 发明授权

US07866533B2 Conductive ball removing method, conductive ball mounting method, conductive ball removing apparatus, and conductive ball mounting apparatus 有权
标题翻译：导电球去除方法，导电球安装方法，导电球去除装置和导电球安装装置
公开(公告)号：US07866533B2
公开(公告)日：2011-01-11
申请号：US12336875
申请日：2008-12-17
申请人： Kazuo Tanaka , Kiyoaki Iida , Hideaki Sakaguchi , Nobuyuki Machida
发明人： Kazuo Tanaka , Kiyoaki Iida , Hideaki Sakaguchi , Nobuyuki Machida
IPC分类号： B23K1/20 , B23K3/06
CPC分类号： B23K3/0623 , H01L24/11 , H01L24/742 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/11005 , H01L2224/11334 , H01L2224/13005 , H01L2224/13147 , H01L2224/1319 , H01L2224/13561 , H01L2224/1357 , H01L2224/136 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H05K3/3478 , H05K2203/0191 , H05K2203/041 , H05K2203/0557 , H01L2924/20751 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： In a method of removing conductive balls that are left on a mask provided on a substrate having pads thereon, the method includes: (a) making a sheet member close to the mask using a contacting mechanism such that a gap between the sheet member and the mask is set small than a diameter of the conductive balls. The conductive balls are removed in such a manner that the conductive balls are adhered onto the sheet member.
摘要翻译：在除去设置在其上具有衬垫的衬底上的掩模上的导电球的方法中，该方法包括：（a）使用接触机构使片状构件靠近掩模，使得片构件和掩模被设定为小于导电球的直径。以这样的方式去除导电球，使得导电球粘附到片状构件上。

16. 发明申请

US20100171177A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100171177A1
公开(公告)日：2010-07-08
申请号：US12727811
申请日：2010-03-19
申请人： Takahiro HAYASHI , Shunsuke Toyoshima , Kazuo Sakamoto , Naozumi Morino , Kazuo Tanaka
发明人： Takahiro HAYASHI , Shunsuke Toyoshima , Kazuo Sakamoto , Naozumi Morino , Kazuo Tanaka
IPC分类号： H01L27/06 , H01L23/58
CPC分类号： H01L23/49844 , H01L23/49811 , H01L23/50 , H01L23/5226 , H01L23/5286 , H01L23/53228 , H01L23/585 , H01L24/05 , H01L24/06 , H01L24/49 , H01L27/0255 , H01L27/092 , H01L2224/02166 , H01L2224/05025 , H01L2224/05093 , H01L2224/05095 , H01L2224/05124 , H01L2224/05624 , H01L2224/06102 , H01L2224/06133 , H01L2224/06143 , H01L2224/06153 , H01L2224/06163 , H01L2224/49105 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/12036 , H01L2924/1306 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
摘要翻译：本发明的目的是提供一种能够减小半导体器件的平面尺寸的技术。在半导体衬底上形成输入/输出电路，接地布线和电源布线通过输入/输出电路，并且在其上形成用于焊盘的导电层。输入/输出电路由nMISFET形成区域和pMISFET形成区域中的MISFET元件形成，电阻元件形成区域中的电阻元件和用作保护元件的二极管元件形成区域中的二极管元件。连接到保护元件并位于接地布线和电源布线下方的布线在nMISFET形成区域和pMISFET形成区域之间以及接地布线和要连接的电源布线之间的拉出区域中拉出到导电层。

17. 发明申请

US20090273870A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20090273870A1
公开(公告)日：2009-11-05
申请号：US12501007
申请日：2009-07-10
申请人： Hiroyasu Ishizuka , Kazuo Tanaka
发明人： Hiroyasu Ishizuka , Kazuo Tanaka
IPC分类号： H02H9/00 , G11C13/04
CPC分类号： H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： The present invention is provided to suppress occurrence of an erroneous operation in a protection circuit due to a relatively small power source fluctuation such as a power source noise. The protection circuit has a first resistor and a capacitor connected in series between a power source line and a ground line, an inverter whose input is connected between the first resistor and the capacitor, and a MOS transistor whose gate electrode receives an output of the inverter and whose drain electrode and source electrode are connected to the power source line and the ground line. When a high voltage fluctuation occurs in the power source line, a level change at a connection point between the first resistor and the capacitor is delayed according to a time constant. By the delay, the MOS transistor that receives an output of the inverter is temporarily turned on and discharges a high voltage to the ground line. Since an output of the inverter is pulled down to the ground line via a second resistor, even if an output of the inverter fluctuates undesirably, fluctuations in a gate input of the MOS transistor are suppressed.
摘要翻译：本发明是为了抑制电源噪声等电源波动较小的问题而抑制保护电路发生错误的动作。保护电路具有串联连接在电源线和地线之间的第一电阻器和电容器，输入端连接在第一电阻器和电容器之间的反相器，以及栅极接收反相器的输出的MOS晶体管并且其漏电极和源电极连接到电源线和接地线。当电源线发生高电压波动时，第一电阻和电容器之间的连接点处的电平变化根据时间常数被延迟。通过延迟，接收逆变器的输出的MOS晶体管暂时导通，并将高电压放电到地线。由于逆变器的输出通过第二电阻被下拉到接地线，所以即使反相器的输出波动不期望，也抑制了MOS晶体管的栅极输入的波动。

18. 发明授权

US07563527B2 Fuel cell-atmospheric-pressure turbine hybrid system 失效
标题翻译：燃料电池 - 大气压涡轮机混合动力系统
公开(公告)号：US07563527B2
公开(公告)日：2009-07-21
申请号：US10553692
申请日：2004-06-29
申请人： Kazuo Tanaka , Eiichi Harada , Takatoshi Shoji , Junichi Kitajima , Seiji Yamashita
发明人： Kazuo Tanaka , Eiichi Harada , Takatoshi Shoji , Junichi Kitajima , Seiji Yamashita
IPC分类号： H01M8/04
CPC分类号： H01M8/04022 , F02C6/00 , F05D2220/60 , H01M8/0662 , H01M16/00
摘要： A fuel cell-atmospheric-pressure turbine hybrid system uses the thermal energy of a cell exhaust gas discharged from an atmospheric-pressure, high-temperature fuel cell effectively, does not need any additional emergency protective device, and enables the use of lightweight, easy-to-process structural and piping materials to reduces the cost.The fuel cell-atmospheric-pressure turbine hybrid system includes: a combustor 2 for burning an exhaust gas G1 discharged from an atmospheric-pressure, high-temperature fuel cell 1; a turbine 3 in which a combustion gas G2 discharged from the combustor 2 expands and the pressure of the combustion gas G2 drops to a negative pressure; a compressor 4 for compressing an exhaust gas G3 discharged from the turbine 3 to increase the pressure of the exhaust gas G3; and a heat exchanger 5 for transferring heat from the high-temperature exhaust gas G3 discharged from the turbine 3 to low-temperature air A to be supplied to the fuel cell 1.
摘要翻译：燃料电池 - 大气压涡轮机混合动力系统有效地利用从大气压高温燃料电池排出的电池废气的热能，不需要任何额外的紧急保护装置，并且能够使用轻便，容易过程结构和管道材料，以降低成本。燃料电池 - 大气压涡轮机混合动力系统包括：燃烧器2，用于燃烧从大气压高温燃料电池1排出的废气G1; 从燃烧器2排出的燃烧气体G2膨胀并且燃烧气体G2的压力下降到负压的涡轮3; 用于压缩从涡轮3排出的废气G3的压缩机4，以增加废气G3的压力; 以及用于将从涡轮机3排出的高温排气G3的热量传递给供给到燃料电池1的低温空气A的热交换器5。

19. 外观设计

USD546394S1 Advertising pillar 有权
标题翻译：广告柱
公开(公告)号：USD546394S1
公开(公告)日：2007-07-10
申请号：US29238431
申请日：2005-09-16
申请人： Kazuo Tanaka , Toshihiko Irie , Haruo Nozaki
设计人： Kazuo Tanaka , Toshihiko Irie , Haruo Nozaki

20. 发明申请

US20060273825A1 Level conversion circuit and semiconductor integrated circuit device employing the level conversion circuit 有权
公开(公告)号：US20060273825A1
公开(公告)日：2006-12-07
申请号：US11484690
申请日：2006-07-12
申请人： Kazuo Tanaka , Hiroyuki Mizuno , Rie Nishiyama , Manabu Miyamoto
发明人： Kazuo Tanaka , Hiroyuki Mizuno , Rie Nishiyama , Manabu Miyamoto
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H01L2924/0002 , H03K3/356104 , H01L2924/00
摘要： In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

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