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11. 发明授权

US06239039B1 Semiconductor wafers processing method and semiconductor wafers produced by the same 有权
标题翻译：半导体晶片加工方法及其制造的半导体晶片
公开(公告)号：US06239039B1
公开(公告)日：2001-05-29
申请号：US09207193
申请日：1998-12-08
申请人： Takashi Nihonmatsu , Seiichi Miyazaki , Masahiko Yoshida , Hideo Kudo , Tadahiro Kato
发明人： Takashi Nihonmatsu , Seiichi Miyazaki , Masahiko Yoshida , Hideo Kudo , Tadahiro Kato
IPC分类号： H01L21302
CPC分类号： H01L21/02052 , H01L21/02019 , H01L21/30604 , H01L21/30608 , Y10S438/928 , Y10S438/959 , Y10S438/974 , Y10S438/977
摘要： A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching. The method can remove a mechanically formed damage layer, improve surface roughness, and efficiently decrease the depth of locally formed deep pits, while the flatness of the wafer attained through lapping is maintained, in order to produce a chemically etched wafer having a smooth and flat etched surface that hardly causes generation particles and contamination.
摘要翻译：处理从单晶锭切片的半导体晶片的方法至少包括倒角，研磨，蚀刻，镜面抛光和清洁的步骤。在蚀刻步骤中，首先进行碱蚀刻，然后进行酸蚀刻，优选进行反应控制的酸蚀刻。碱蚀刻的蚀刻量大于酸蚀刻的蚀刻量。或者，在蚀刻步骤中，首先进行反应控制的酸蚀刻，然后进行扩散控制的酸蚀刻。反应控制的酸蚀刻的蚀刻量大于扩散控制的酸蚀刻的蚀刻量。该方法可以去除机械形成的损伤层，提高表面粗糙度，并有效降低局部形成的深坑的深度，同时通过研磨获得的晶片的平整度得以保持，以便产生具有光滑平坦的化学蚀刻晶片蚀刻的表面几乎不引起发生颗粒和污染。

12. 发明授权

US07268047B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07268047B2
公开(公告)日：2007-09-11
申请号：US11357072
申请日：2006-02-21
申请人： Tsunetoshi Arikado , Takaaki Kawahara , Kazuyoshi Torii , Hiroshi Kitajima , Seiichi Miyazaki
发明人： Tsunetoshi Arikado , Takaaki Kawahara , Kazuyoshi Torii , Hiroshi Kitajima , Seiichi Miyazaki
IPC分类号： H01L21/336
CPC分类号： H01L21/28185 , H01L21/28194 , H01L29/513 , H01L29/517 , H01L29/7833
摘要： A gate insulating film on a silicon substrate of includes a SiO2 film and a high-k film. The high-k film contains a transition metal, aluminum, silicon, and oxygen. The concentration of silicon in the high-k film is higher than the concentrations of the transition metal and aluminum in the vicinity of the interface with the SiO2 film and the vicinity of the interface with the gate electrode. Furthermore, it is preferable that the concentration of silicon is the highest at least in one of the vicinity of the interface with the SiO2 film or the vicinity of the interface with the gate electrode, gradually decreases with distance from these interfaces, and becomes the lowest in a central part of the high-k film.
摘要翻译：硅衬底上的栅极绝缘膜包括SiO 2膜和高k膜。高k膜含有过渡金属，铝，硅和氧。高k膜中的硅的浓度高于与SiO 2膜的界面附近的过渡金属和铝的浓度以及与栅电极的界面附近的浓度。此外，优选至少在与SiO 2膜的界面附近或与栅电极的界面附近的硅中的浓度最高，随着距离逐渐减小从这些界面，并成为高k电影中心部分中最低的。

13. 发明申请

US20060138572A1 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060138572A1
公开(公告)日：2006-06-29
申请号：US11357072
申请日：2006-02-21
申请人： Tsunetoshi Arikado , Takaaki Kawahara , Kazuyoshi Torii , Hiroshi Kitajima , Seiichi Miyazaki
发明人： Tsunetoshi Arikado , Takaaki Kawahara , Kazuyoshi Torii , Hiroshi Kitajima , Seiichi Miyazaki
IPC分类号： H01L21/8238
CPC分类号： H01L21/28185 , H01L21/28194 , H01L29/513 , H01L29/517 , H01L29/7833
摘要： A gate insulating film on a silicon substrate of includes a SiO2 film and a high-k film. The high-k film contains a transition metal, aluminum, silicon, and oxygen. The concentration of silicon in the high-k film is higher than the concentrations of the transition metal and aluminum in the vicinity of the interface with the SiO2 film and the vicinity of the interface with the gate electrode. Furthermore, it is preferable that the concentration of silicon is the highest at least in one of the vicinity of the interface with the SiO2 film or the vicinity of the interface with the gate electrode, gradually decreases with distance from these interfaces, and becomes the lowest in a central part of the high-k film.
摘要翻译：硅衬底上的栅极绝缘膜包括SiO 2膜和高k膜。高k膜含有过渡金属，铝，硅和氧。高k膜中的硅的浓度高于与SiO 2膜的界面附近的过渡金属和铝的浓度以及与栅电极的界面附近的浓度。此外，优选至少在与SiO 2膜的界面附近或与栅电极的界面附近的硅中的浓度最高，随着距离逐渐减小从这些界面，并成为高k电影中心部分中最低的。

14. 发明授权

US4153848A Receiver circuit 失效
标题翻译：接收电路
公开(公告)号：US4153848A
公开(公告)日：1979-05-08
申请号：US813296
申请日：1977-07-06
申请人： Seiichi Miyazaki
发明人： Seiichi Miyazaki
IPC分类号： H03K5/08 , H03K5/15 , H04L25/22 , H03K5/01 , H03K5/153
CPC分类号： H03K5/08 , H03K5/15 , H04L25/22
摘要： A receiver circuit for receiving a double current pulse signal from a transmission line and delivering positive pulse or a negative pulse corresponding to that of the double current pulse signal in a discriminating manner. The circuit comprises an input transformer having a secondary winding divided into two halves; a resistor connected in series with each output terminal of the input transformer and having a resistance value which is considerably higher than a characteristic impedance of the transmission line; a diode having a cathode connected to an output terminal of the resistor and an anode connected to ground; and an amplifier having input terminals connected to the resistor and the diode, respectively, and delivering either a positive pulse or a negative pulse corresponding to that of the double current pulse signal in a discriminating manner.
摘要翻译：一种用于从传输线接收双电流脉冲信号并以辨别方式传送与双电流脉冲信号对应的正脉冲或负脉冲的接收器电路。该电路包括具有被分成两半的次级绕组的输入变压器; 与输入变压器的每个输出端串联连接的电阻器，其电阻值远高于传输线的特性阻抗; 具有连接到电阻器的输出端子的阴极和连接到地的阳极的二极管; 以及放大器，其输入端分别连接到电阻器和二极管，并且以鉴别方式传送与双电流脉冲信号的正脉冲或负脉冲相对应的正脉冲或负脉冲。

15. 发明授权

US4078228A Loop data highway communication system 失效
标题翻译：环路数据通信系统
公开(公告)号：US4078228A
公开(公告)日：1978-03-07
申请号：US667415
申请日：1976-03-16
申请人： Seiichi Miyazaki
发明人： Seiichi Miyazaki
IPC分类号： H04L12/43 , H04Q11/00
CPC分类号： H04L12/43
摘要： A plurality of data stations are connected in series by a "transmission line" to form a loop data communication system through which signals are transmitted unidirectionally. The transmission of the data is effected by using an information block containing two frames A and B as one unit. A central data station among the plurality of data stations is constructed to retransmit the received contents of frame A by frame B. The transmitting data station transmits the information by inserting it in frame A and an addressed data station receives the content of frame B.
摘要翻译：多个数据站通过“传输线”串联连接以形成环路数据通信系统，通过该系统单向传输信号。通过使用包含两帧A和B的信息块作为一个单元来实现数据的传输。多个数据站之间的中央数据站被构造为通过帧B重传帧A的接收内容。发送数据站通过将其插入到帧A中来发送信息，并且寻址的数据站接收帧B的内容。

16. 发明授权

US07250368B2 Semiconductor wafer manufacturing method and wafer 有权
标题翻译：半导体晶圆制造方法和晶圆
公开(公告)号：US07250368B2
公开(公告)日：2007-07-31
申请号：US10512637
申请日：2003-04-24
申请人： Takahiro Kida , Seiichi Miyazaki , Kazuhiko Nishimura , Nobuyuki Hayashi , Katsunori Arai
发明人： Takahiro Kida , Seiichi Miyazaki , Kazuhiko Nishimura , Nobuyuki Hayashi , Katsunori Arai
IPC分类号： H01L21/304
CPC分类号： H01L21/02008 , B24B9/065 , B24B37/042 , H01L21/02052 , H01L21/30604 , Y10S438/928
摘要： The present invention provides a method for manufacturing a semiconductor wafer capable of manufacturing a wafer without ring-like sag in an outer peripheral portion thereof when polishing an alkali etched wafer, and a wafer without the ring-like sag in an outer peripheral portion thereof. The present invention comprises: a back surface part polishing and edge polishing step for performing back surface part polishing and edge polishing such that mirror polishing is performed on a chamfered portion and an inner part extending inward from a boundary between the chamfered portion and a back surface of a starting wafer; and a front surface polishing step for mirror polishing a front surface of the wafer subjected to the back surface part polishing and edge polishing step holding the wafer by the back surface thereof.
摘要翻译：本发明提供了一种制造半导体晶片的方法，该半导体晶片在其外周部分研磨碱蚀刻晶片时，并且在其外周部分中没有环状凹陷的晶片，能够在其外周部分制造没有环状凹陷的晶片。本发明包括：背面部分抛光和边缘抛光步骤，用于进行背面部分抛光和边缘抛光，使得在倒角部分和从倒角部分和背面之间的边界向内延伸的内部部分进行镜面抛光的起始晶圆; 以及前表面抛光步骤，用于对经过后表面抛光的晶片的前表面进行镜面抛光和通过其后表面保持晶片的边缘抛光步骤。

17. 发明授权

US06346485B1 Semiconductor wafer processing method and semiconductor wafers produced by the same 失效
标题翻译：半导体晶片处理方法及其制造的半导体晶片
公开(公告)号：US06346485B1
公开(公告)日：2002-02-12
申请号：US09633401
申请日：2000-08-07
申请人： Takashi Nihonmatsu , Seiichi Miyazaki , Masahiko Yoshida , Hideo Kudo , Tadahiro Kato
发明人： Takashi Nihonmatsu , Seiichi Miyazaki , Masahiko Yoshida , Hideo Kudo , Tadahiro Kato
IPC分类号： H01L21461
CPC分类号： H01L21/02052 , H01L21/02019 , H01L21/30604 , H01L21/30608 , Y10S438/928 , Y10S438/959 , Y10S438/974 , Y10S438/977
摘要： A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching. The method can remove a mechanically formed damage layer, improve surface roughness, and efficiently decrease the depth of locally formed deep pits, while the flatness of the wafer attained through lapping is maintained, in order to produce a chemically etched wafer having a smooth and flat etched surface that hardly causes generation particles and contamination.
摘要翻译：处理从单晶锭切片的半导体晶片的方法至少包括倒角，研磨，蚀刻，镜面抛光和清洁的步骤。在蚀刻步骤中，首先进行碱蚀刻，然后进行酸蚀刻，优选进行反应控制的酸蚀刻。碱蚀刻的蚀刻量大于酸蚀刻的蚀刻量。或者，在蚀刻步骤中，首先进行反应控制的酸蚀刻，然后进行扩散控制的酸蚀刻。反应控制的酸蚀刻的蚀刻量大于扩散控制的酸蚀刻的蚀刻量。该方法可以去除机械形成的损伤层，提高表面粗糙度，并有效降低局部形成的深坑的深度，同时通过研磨获得的晶片的平整度得以保持，以便产生具有光滑平坦的化学蚀刻晶片蚀刻的表面几乎不引起发生颗粒和污染。

18. 发明授权

US5784373A Switching device for LAN 失效
标题翻译： LAN交换设备
公开(公告)号：US5784373A
公开(公告)日：1998-07-21
申请号：US604015
申请日：1996-02-20
申请人： Tadashi Satake , Seiichi Miyazaki , Mario Cardona
发明人： Tadashi Satake , Seiichi Miyazaki , Mario Cardona
IPC分类号： H04L12/18 , H04L12/56 , H04J3/26 , H04L12/46
CPC分类号： H04L12/18 , H04L12/5601 , H04L49/351 , H04L49/201
摘要： A switching device for LAN is provided for switching packets in ETHERNET. The switching device includes an arrangement for storing the packet received at one of a plurality of receiving ports respectively connected to ETHERNET segments in a receiving buffer commonly used by the whole of the device, by means of a storage device of the receiving buffer. A transmitting destination port for the packet is determined through the use of an address filter device also common for the whole device. A transmitting buffer includes a storage device which receives the packet from the receiving buffer. Then, the packet is transferred from the storage device of the transmitting buffer to one of a plurality of transmitting ports corresponding to the determined address.
摘要翻译：提供用于LAN的交换设备用于在以太网中切换分组。切换装置包括一种装置，用于通过接收缓冲器的存储装置来存储在分别连接到整个装置通常使用的接收缓冲器中的以太网段的多个接收端口之一处接收的分组。通过使用对于整个设备也是公共的地址过滤器设备来确定分组的发送目的地端口。发送缓冲器包括从接收缓冲器接收分组的存储装置。然后，将分组从发送缓冲器的存储装置传送到与确定的地址对应的多个发送端口中的一个。

19. 发明授权

US4121118A Bipolar signal generating apparatus 失效
标题翻译：双极信号发生装置
公开(公告)号：US4121118A
公开(公告)日：1978-10-17
申请号：US813241
申请日：1977-07-06
申请人： Seiichi Miyazaki
发明人： Seiichi Miyazaki
IPC分类号： H03K5/151 , H03K17/60 , H04L25/02 , H04L25/08 , H04L25/49 , H03K5/20 , H03K13/24
CPC分类号： H04L25/028 , H03K17/601 , H03K5/151 , H04L25/0266 , H04L25/0272 , H04L25/08 , H04L25/4925
摘要： A bipolar signal generating apparatus for generating a bipolar signal having positive and negative polarities and comprising a switch means for connecting two terminals of a primary winding of a transformer with each other when the bipolar signal has a level of its neutral region.
摘要翻译：一种双极性信号发生装置，用于产生具有正极性和负极性的双极性信号，并且当双极性信号具有其中性区域的电平时，包括用于将变压器的初级绕组的两个端子彼此连接的开关装置。

20. 发明申请

US20050142882A1 Semiconductor water manufacturing method and wafer 有权
标题翻译：半导体水处理方法及晶圆
公开(公告)号：US20050142882A1
公开(公告)日：2005-06-30
申请号：US10512637
申请日：2003-04-24
申请人： Takahiro Kida , Seiichi Miyazaki , Kazuhiko Nishimura , Nobuyuki Hayashi , Katsunori Arai
发明人： Takahiro Kida , Seiichi Miyazaki , Kazuhiko Nishimura , Nobuyuki Hayashi , Katsunori Arai
IPC分类号： B24B9/00 , B24B9/06 , B24B37/04 , H01L21/302 , H01L21/304 , H01L21/306 , H01L21/461
CPC分类号： H01L21/02008 , B24B9/065 , B24B37/042 , H01L21/02052 , H01L21/30604 , Y10S438/928
摘要： The present invention provides a method for manufacturing a semiconductor wafer capable of manufacturing a wafer without ring-like sag in an outer peripheral portion thereof when polishing an alkali etched wafer, and a wafer without the ring-like sag in an outer peripheral portion thereof. The present invention comprises: a back surface part polishing and edge polishing step for performing back surface part polishing and edge polishing such that mirror polishing is performed on a chamfered portion and an inner part extending inward from a boundary between the chamfered portion and a back surface of a starting wafer; and a front surface polishing step for mirror polishing a front surface of the wafer subjected to the back surface part polishing and edge polishing step holding the wafer by the back surface thereof.
摘要翻译：本发明提供了一种制造半导体晶片的方法，该半导体晶片在其外周部分研磨碱蚀刻晶片时，并且在其外周部分中没有环状凹陷的晶片，能够在其外周部分制造没有环状凹陷的晶片。本发明包括：背面部分抛光和边缘抛光步骤，用于进行背面部分抛光和边缘抛光，使得在倒角部分和从倒角部分和背面之间的边界向内延伸的内部部分进行镜面抛光的起始晶圆; 以及前表面抛光步骤，用于对经过后表面抛光的晶片的前表面进行镜面抛光和通过其后表面保持晶片的边缘抛光步骤。

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