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11. 发明授权

US5036453A Master/slave sequencing processor 失效
标题翻译：主/从排序处理器
公开(公告)号：US5036453A
公开(公告)日：1991-07-30
申请号：US390507
申请日：1989-08-02
申请人： Karl Renner , John P. Shanklin
发明人： Karl Renner , John P. Shanklin
IPC分类号： G06F15/80
CPC分类号： G06F15/8015
摘要： An array processor includes a master array controller and sequencer (12) and a plurality of slave processors (20a)-(20n). The master generates sequencing commands for sequencing instruction flow in each of the slave processors. The slave processors generate addresses for associated memories (34a)-(34n). The data outputs of the memories are interfaced through a cross point switch (22) to a slave data processor (24). The master (12) is operable to initialize all of the slave devices to a starting address for an internal routine and sequence the instruction flow therein in a synchronous and parallel manner to execute a particular task.
摘要翻译：阵列处理器包括主阵列控制器和定序器（12）和多个从属处理器（20a） - （20n）。主机产生用于对每个从属处理器中的指令流进行排序的排序命令。从处理器产生相关存储器（34a） - （34n）的地址。存储器的数据输出通过交叉点开关（22）连接到从属数据处理器（24）。主机（12）可操作以将所有从机设备初始化为内部程序的起始地址，并以同步和并行方式对其中的指令流进行排序，以执行特定任务。

12. 发明申请

US20110131439A1 Jitter Precorrection Filter in Time-Average-Frequency Clocked Systems 有权
标题翻译：时间平均频率时钟系统中的抖动预校正滤波器
公开(公告)号：US20110131439A1
公开(公告)日：2011-06-02
申请号：US12628339
申请日：2009-12-01
申请人： Karl Renner , Walter Heinrich Demmer , Liming Xiu
发明人： Karl Renner , Walter Heinrich Demmer , Liming Xiu
IPC分类号： H03L7/06 , H03M1/82 , H03L7/00 , G06F1/08
CPC分类号： G06F1/08 , H03L7/18
摘要： Synchronous circuitry for processing digital data in which the data are filtered to compensate for expected jitter in time-average frequency clock signals. Time-average frequency synthesis circuitry generates internal clock signals of a desired frequency, for example as based on a recovered clock signal from an input data stream, in a manner in which not all periods of the clock signal are of uniform duration. A jitter precorrection filter is inserted into the data path to apply a variable delay to pre-correct for distortion caused by jitter in the clock cycle. In embodiments of the invention using a flying-adder architecture to generate the clock signal, coefficients of the digital filer realizing the jitter precorrection filter are calculated according to the currently-selected oscillator phase and according to a fractional portion of a digital frequency control word.
摘要翻译：用于处理数字数据的同步电路，其中数据被滤波以补偿时间平均频率时钟信号中的预期抖动。时间平均频率合成电路以不是所有的时钟信号周期具有均匀持续时间的方式，例如基于来自输入数据流的恢复的时钟信号来产生期望频率的内部时钟信号。抖动预校正滤波器被插入到数据路径中以应用可变延迟来预校正由时钟周期中的抖动引起的失真。在使用飞加法器架构来生成时钟信号的本发明的实施例中，根据当前选择的振荡器相位并根据数字频率控制字的小数部分来计算实现抖动预校正滤波器的数字滤波器的系数。

13. 发明授权

US07443454B2 Method for treating inter-frame motion in a composite video signal 有权
标题翻译：在复合视频信号中处理帧间运动的方法
公开(公告)号：US07443454B2
公开(公告)日：2008-10-28
申请号：US11240718
申请日：2005-10-01
申请人： Ramesh M. Chandrasekaran , Weider Peter Chang , Karl Renner
发明人： Ramesh M. Chandrasekaran , Weider Peter Chang , Karl Renner
IPC分类号： H04N9/78 , H04N5/21
CPC分类号： H04N5/144
摘要： A method for treating inter-frame motion in a series of consecutive signal frames of a composite video signal includes the steps of, for an evaluation pixel position in each frame of a test frame-set including three successive signal frames: (a) determining whether there is at least a predetermined difference in chroma component or in luma component signals at the evaluation pixel; (b) if in step (a) there is not a predetermined difference in chroma component signals or in luma component signals, determining whether a first and third frame of the test frame-set are substantially identical; (c) determining whether at least a first predetermined number of the luma or chroma component signals in the test frame-set present at least one false color; and (d) determining whether at least a second predetermined number of high frequency luma component signals exist in the test frame-set.
摘要翻译：一种用于处理复合视频信号的一系列连续信号帧中的帧间运动的方法包括以下步骤：对于包括三个连续信号帧的测试帧集合的每个帧中的评估像素位置：（a）确定是否评估像素处的色度分量或亮度分量信号中至少存在预定的差异; （b）如果在步骤（a）中色度分量信号或亮度分量信号中没有预定的差异，则确定测试帧组的第一和第三帧是否基本相同; （c）确定测试帧组中至少第一预定数量的亮度或色度分量信号是否存在至少一种假色; 和（d）确定在测试帧组中是否存在至少第二预定数量的高频亮度分量信号。

14. 发明授权

US06188788B1 Automatic color saturation control in video decoder using recursive algorithm 有权
标题翻译：使用递归算法在视频解码器中进行自动色彩饱和度控制
公开(公告)号：US06188788B1
公开(公告)日：2001-02-13
申请号：US09196825
申请日：1998-11-20
申请人： Karl Renner , Weider Peter Chang
发明人： Karl Renner , Weider Peter Chang
IPC分类号： G06K900
CPC分类号： H04N9/68 , A61K2039/5254 , A61K2039/5256
摘要： A method for automatic color gain control utilizes a plurality of process blocks which compare the measured burst amplitude with an ideal burst amplitude, and then generate necessary scaling factors to automatically control the gain. Each of the process blocks utilizes recursive relationships for accumulating values, which recursive relationships require no multiplications but, rather, require only additions and/or subtractions, which additions and/or subtractions require merely an adder with a change of sign. A scale value is generated which represents the ratio of the measure to ideal burst amplitude value, which is then utilized to generate Cr and Cb in a YCrCb digitized format. This is utilized to scale the U and the V values in a YUV digitized format.
摘要翻译：用于自动色彩增益控制的方法利用多个处理块，将多个处理块与测量的突发幅度与理想的突发幅度进行比较，然后产生必要的缩放因子以自动控制增益。每个进程块利用用于累加值的递归关系，递归关系不需要乘法，而是仅需要加法和/或减法，这些加法和/或减法仅需要具有符号变化的加法器。产生一个比例值，其表示测量与理想脉冲串幅度值的比率，然后用于产生YCrCb数字化格式的Cr和Cb。这用于以YUV数字化格式缩放U值和V值。

15. 发明授权

US08195972B2 Jitter precorrection filter in time-average-frequency clocked systems 有权
标题翻译：时频平均频率系统中的抖动预校正滤波器
公开(公告)号：US08195972B2
公开(公告)日：2012-06-05
申请号：US12628339
申请日：2009-12-01
申请人： Karl Renner , Walter Heinrich Demmer , Liming Xiu
发明人： Karl Renner , Walter Heinrich Demmer , Liming Xiu
IPC分类号： G06F1/00 , G06F1/04 , G06F11/00 , H03L7/06
CPC分类号： G06F1/08 , H03L7/18
摘要： Synchronous circuitry for processing digital data in which the data are filtered to compensate for expected jitter in time-average frequency clock signals. Time-average frequency synthesis circuitry generates internal clock signals of a desired frequency, for example as based on a recovered clock signal from an input data stream, in a manner in which not all periods of the clock signal are of uniform duration. A jitter precorrection filter is inserted into the data path to apply a variable delay to pre-correct for distortion caused by jitter in the clock cycle. In embodiments of the invention using a flying-adder architecture to generate the clock signal, coefficients of the digital filer realizing the jitter precorrection filter are calculated according to the currently-selected oscillator phase and according to a fractional portion of a digital frequency control word.
摘要翻译：用于处理数字数据的同步电路，其中数据被滤波以补偿时间平均频率时钟信号中的预期抖动。时间平均频率合成电路以不是所有的时钟信号周期具有均匀持续时间的方式，例如基于来自输入数据流的恢复的时钟信号来产生期望频率的内部时钟信号。抖动预校正滤波器被插入到数据路径中以应用可变延迟来预校正由时钟周期中的抖动引起的失真。在使用飞加法器架构来生成时钟信号的本发明的实施例中，根据当前选择的振荡器相位并根据数字频率控制字的小数部分来计算实现抖动预校正滤波器的数字滤波器的系数。

16. 发明授权

US07362380B2 Equilibrium based vertical sync phase lock loop for video decoder 有权
标题翻译：用于视频解码器的基于平衡的垂直同步锁相环
公开(公告)号：US07362380B2
公开(公告)日：2008-04-22
申请号：US10616754
申请日：2003-07-10
申请人： Karl Renner , Walter Heinrich Demmer
发明人： Karl Renner , Walter Heinrich Demmer
IPC分类号： H03L7/00
CPC分类号： H04N5/126 , H03L7/0991
摘要： The present invention discloses a PLL (90), which may be implemented in software, hardware, or a combination of software and hardware, which comprises a sync detector (92), a loop filter (94), a vertical sync discrete time oscillator (DTO) (98), and an output logic (100) adapted to detect a vertical sync (222), wherein the loop filter (94), the vertical sync DTO (98), and the output logic (100) are coupled to the sync detector (92).
摘要翻译：本发明公开了一种PLL（90），其可以以软件，硬件或软件和硬件的组合来实现，其包括同步检测器（92），环路滤波器（94），垂直同步离散时间振荡器 DTO）（98）和适于检测垂直同步（222）的输出逻辑（100），其中环路滤波器（94），垂直同步DTO（98）和输出逻辑（100）耦合到同步检测器（92）。

17. 发明授权

US06690784B2 Caller select with memory for telephone number programming and review 失效
标题翻译：来电者选择内存进行电话号码编程和审查
公开(公告)号：US06690784B2
公开(公告)日：2004-02-10
申请号：US09681240
申请日：2001-03-03
申请人： Karl Renner , Darwin Renner
发明人： Karl Renner , Darwin Renner
IPC分类号： H04M342
CPC分类号： H04M1/57 , H04M1/663 , H04M3/436
摘要： Caller Select allows the user to select incoming telephone numbers in the Caller ID that he wishes to receive and will ring the telephone 34; all other numbers will be rejected and not allowed to ring the telephone 34. Numbers may programmed either by pressing an enter switch 24 during a review controlled by a switch 26 or by going into the program mode by pressing a mode switch 22 and pressing buttons on a touch tone phone 34. The operation is controlled by software running in a low power microprocessor 16. The Caller Select mode may be turned off by a switch 28 which in display of the Caller ID only and ringing by all calls.
摘要翻译：呼叫者选择允许用户选择他希望接收的来电显示中的接收电话号码，并且将响电话34; 所有其他数字将被拒绝并且不允许振铃电话34.数字可以通过在由开关26控制的检查期间按下输入开关24或者通过按下模式开关22并按下按钮进入程序模式来编程触摸音电话34.该操作由在低功率微处理器16中运行的软件控制。呼叫者选择模式可以由开关28关闭，开关28仅在来自主叫ID的显示和所有呼叫振铃。

18. 发明授权

US4745544A Master/slave sequencing processor with forced I/O 失效
标题翻译：具有强制I / O的主/从排序处理器
公开(公告)号：US4745544A
公开(公告)日：1988-05-17
申请号：US809095
申请日：1985-12-12
申请人： Karl Renner , John P. Shanklin
发明人： Karl Renner , John P. Shanklin
IPC分类号： G06F15/173 , G06F15/80 , G06F15/16
CPC分类号： G06F15/17375 , G06F15/8015
摘要： An array processor operating in the forced I/O mode includes a master controller (12) for generating sequenced commands for output to slave address generators (52) (54) and (62). The slave (52) and (54) operate in a data processing and a forced I/O mode. Each of the slaves have a set of data instructions and a set of I/O instructions therein. The data instructions are sequenced through in accordance with the sequenced commands generated by the master controller (12) synchronously and in parallel with the other slaves to generate addresses for memories (76) and (80). The master controller (12) initiates the I/O mode with runs independent and asychronously with respect to the sequenced commands to interface with an external I/O device (98). This data is transferred to the associated data memory and, when full, the operation alternates such that the other slave is in the I/O mode and the other data memory is utilized for storing I/O data.
摘要翻译：以强制I / O模式运行的阵列处理器包括主控制器（12），用于产生用于输出到从地址发生器（52）（54）和（62）的顺序命令。从机（52）和（54）在数据处理和强制I / O模式下工作。每个从站都有一组数据指令和一组I / O指令。数据指令通过根据由主控制器（12）同步并与其它从机产生的排序命令进行排序，以产生存储器（76）和（80）的地址。主控制器（12）相对于与外部I / O设备（98）接口的排序命令，以独立运行和非同步方式启动I / O模式。该数据被传送到关联的数据存储器，并且在完成时，操作交替使得另一个从机处于I / O模式，而另一个数据存储器用于存储I / O数据。

19. 发明授权

US06943847B2 FM demodulator for SECAM decoder 有权
标题翻译： FM解调器用于SECAM解码器
公开(公告)号：US06943847B2
公开(公告)日：2005-09-13
申请号：US10229717
申请日：2002-08-28
申请人： Karl Renner , Walter Demmer
发明人： Karl Renner , Walter Demmer
IPC分类号： H04N9/66 , H04N11/18 , H04N5/455
CPC分类号： H04N9/66 , H04N11/186
摘要： A SECAM decoder and an FM modulator therefor are disclosed, in which a demodulated color signal is provided to indicate deviations in the frequency of modulated color information from a nominal subcarrier frequency. The demodulator comprises numerator and denominator filters operating on the modulated color information, and a divider providing a ratio result by dividing the numerator filter output by the denominator filter output. The demodulator may include two sets of numerator and denominator filters offset in phase from one another, where one of the two sets is selectively employed in order to mitigate divide-by-zero problems. Also disclosed are methods for demodulating digitized FM color signals in a SECAM decoder.
摘要翻译：公开了一种SECAM解码器及其FM调制器，其中提供解调的彩色信号以指示调制的颜色信息的频率与标称副载波频率的偏差。解调器包括对调制的色彩信息进行操作的分子和分母滤波器，以及通过用分母滤波器输出除以分子滤波器输出而提供比例结果的分频器。解调器可以包括两组相互偏移的分子和分母滤波器，其中选择性地使用两组中的一组来减轻除零问题。还公开了在SECAM解码器中解调数字化FM彩色信号的方法。

20. 发明申请

US20050007493A1 Equilibrium based vertical sync phase lock loop for video decoder 有权
标题翻译：用于视频解码器的基于平衡的垂直同步锁相环
公开(公告)号：US20050007493A1
公开(公告)日：2005-01-13
申请号：US10713714
申请日：2003-11-14
申请人： Karl Renner , Walter Demmer
发明人： Karl Renner , Walter Demmer
IPC分类号： H03L7/00 , H03L7/099 , H04N5/12
CPC分类号： H03L7/0991 , H04N5/126
摘要： The present invention discloses a PLL (90), which may be implemented in software, hardware, or a combination of software and hardware, which comprises a sync detector (92) adapted to output a phase error (152), a vertical sync discrete time oscillator (DTO) block (98) adapted to output a vertical sync DTO (130) based on the phase error (152), and an output logic (100) adapted to detect a vertical sync based on the vertical sync DTO (130).
摘要翻译：本发明公开了一种PLL（90），其可以以软件，硬件或软件和硬件的组合来实现，其包括适于输出相位误差（152）的同步检测器（92），垂直同步离散时间适于基于相位误差（152）输出垂直同步DTO（130）的振荡器（DTO）块（98），以及适于基于垂直同步DTO检测垂直同步的输出逻辑（130）（130）。

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