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11. 发明申请

US20070224757A1 OFFSET VERTICAL DEVICE 失效
标题翻译：偏移垂直装置
公开(公告)号：US20070224757A1
公开(公告)日：2007-09-27
申请号：US11756927
申请日：2007-06-01
申请人： Kangguo Cheng , Ramachandra Divakaruni , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Geng Wang
IPC分类号： H01L21/8242
CPC分类号： H01L27/10867 , H01L27/1087 , H01L29/66181 , H01L29/945
摘要： The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor and a first underlying capacitor that are in electrical contact to each other through a first buried strap, where the first buried strap positioned on a first collar region; and at least one second-type memory cell, where each of the at least are second-type memory device comprises a second transistor and a second underlying capacitor that are in electrical contact through an offset buried strap, where the offset buried strap is positioned on a second collar region, wherein the second collar region has a length equal to the first collar region.
摘要翻译：本发明包括一种用于形成存储器阵列的方法和由其制成的存储器阵列。具体而言，存储器阵列包括至少一个第一型存储器件，至少一个第一型存储器件中的每一个包括通过第一掩埋带彼此电接触的第一晶体管和第一底层电容器，其中位于第一环区的第一掩埋带; 以及至少一个第二类型存储单元，其中至少第二类型存储器件中的每一个包括第二晶体管和第二底层电容器，所述第二晶体管和第二底层电容器通过偏移掩埋带电接触，其中所述偏移掩埋带位于第二衣领区域，其中第二衣领区域具有等于第一衣领区域的长度。

12. 发明申请

US20090047756A1 DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 失效
标题翻译：双端口增益单元与侧面和顶部读取晶体管
公开(公告)号：US20090047756A1
公开(公告)日：2009-02-19
申请号：US12254960
申请日：2008-10-21
申请人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
发明人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
IPC分类号： H01L21/84 , H01L21/8242
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

13. 发明授权

US07459743B2 Dual port gain cell with side and top gated read transistor 有权
标题翻译：双端口增益单元，具有侧和顶栅控读取晶体管
公开(公告)号：US07459743B2
公开(公告)日：2008-12-02
申请号：US11161962
申请日：2005-08-24
申请人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
发明人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

14. 发明授权

US07790530B2 Dual port gain cell with side and top gated read transistor 失效
标题翻译：双端口增益单元，具有侧和顶栅控读取晶体管
公开(公告)号：US07790530B2
公开(公告)日：2010-09-07
申请号：US12254960
申请日：2008-10-21
申请人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
发明人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
IPC分类号： H01L21/00
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

15. 发明授权

US07732872B2 Integration scheme for multiple metal gate work function structures 失效
标题翻译：多金属门功能结构的集成方案
公开(公告)号：US07732872B2
公开(公告)日：2010-06-08
申请号：US11924053
申请日：2007-10-25
申请人： Kangguo Cheng , Michael P. Chudzik , Ramachandra Divakaruni , Geng Wang , Robert C. Wong , Haining S. Yang
发明人： Kangguo Cheng , Michael P. Chudzik , Ramachandra Divakaruni , Geng Wang , Robert C. Wong , Haining S. Yang
IPC分类号： H01L27/088
CPC分类号： H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1116 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.
摘要翻译：在高k栅极电介质层上形成包含具有中带隙功函数的金属层的金属栅极堆叠。在高k栅介质层的一部分上形成阈值电压调整氧化物层，以提供在第一带隙边缘附近具有功函数的器件，而高k电介质层的另一部分保持没有阈值电压调整氧化层。还可以形成包含半导体氧化物基栅极电介质和掺杂多晶半导体材料的栅极堆叠，以提供具有位于与第一带隙边缘相反的第二带隙边缘附近的又一功能功能的栅极堆叠。在包含阈值电压调整氧化物层的区域中形成包含具有中带功函数的p型和n型晶体管的密集电路。

16. 发明申请

US20050224852A1 Offset vertical device 失效
标题翻译：偏移垂直装置
公开(公告)号：US20050224852A1
公开(公告)日：2005-10-13
申请号：US10813352
申请日：2004-03-30
申请人： Kangguo Cheng , Ramachandra Divakaruni , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Geng Wang
IPC分类号： H01L21/334 , H01L21/8242 , H01L27/108 , H01L29/94
CPC分类号： H01L27/10867 , H01L27/1087 , H01L29/66181 , H01L29/945
摘要： The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor and a first underlying capacitor that are in electrical contact to each other through a first buried strap, where the first buried strap positioned on a first collar region; and at least one second-type memory cell, where each of the at least are second-type memory device comprises a second transistor and a second underlying capacitor that are in electrical contact through an offset buried strap, where the offset buried strap is positioned on a second collar region, wherein the second collar region has a length equal to the first collar region.
摘要翻译：本发明包括一种用于形成存储器阵列的方法和由其制成的存储器阵列。具体而言，存储器阵列包括至少一个第一型存储器件，至少一个第一型存储器件中的每一个包括通过第一掩埋带彼此电接触的第一晶体管和第一底层电容器，其中位于第一环区的第一掩埋带; 以及至少一个第二类型存储单元，其中至少第二类型存储器件中的每一个包括第二晶体管和第二底层电容器，所述第二晶体管和第二底层电容器通过偏移掩埋带电接触，其中所述偏移掩埋带位于第二衣领区域，其中第二衣领区域具有等于第一衣领区域的长度。

17. 发明授权

US07785959B2 Method of multi-port memory fabrication with parallel connected trench capacitors in a cell 失效
标题翻译：在单元中并联连接沟槽电容器的多端口存储器制造方法
公开(公告)号：US07785959B2
公开(公告)日：2010-08-31
申请号：US12316748
申请日：2008-12-16
申请人： Kangguo Cheng , Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens , Geng Wang
IPC分类号： H01L21/8242
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage.
摘要翻译：提供了一种用于制造其中多个并联电容器在单元中的多端口存储器的方法。形成多个沟槽电容器，其具有沿多个沟槽的壁延伸的电容器电介质层，所述多个沟槽电容器具有第一电容器板和与第一电容器板相对的电容器电介质层的第二电容器板。第一电容器板导电地连接在一起，并且第二电容器板被导电地连接在一起。以这种方式，第一电容器板适于接收相同的可变电压，并且第二电容器板适于接收相同的固定电压。

18. 发明申请

US20100283093A1 Structure and Method to Form EDRAM on SOI Substrate 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US20100283093A1
公开(公告)日：2010-11-11
申请号：US12437242
申请日：2009-05-07
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L27/10 , H01L21/02
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

19. 发明授权

US07791124B2 SOI deep trench capacitor employing a non-conformal inner spacer 失效
标题翻译： SOI深沟槽电容器采用非保形内隔板
公开(公告)号：US07791124B2
公开(公告)日：2010-09-07
申请号：US12124186
申请日：2008-05-21
申请人： Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Geng Wang
发明人： Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L29/945 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L29/66181
摘要： A bottle shaped trench for an SOI capacitor is formed by a simple processing sequence. A non-conformal dielectric layer with an optional conformal dielectric diffusion barrier layer underneath is formed on sidewalls of a deep trench. Employing an isotropic etch, the non-conformal dielectric layer is removed from a bottom portion of the deep trench, leaving a dielectric spacer covering sidewalls of the buried insulator layer and the top semiconductor layer. The bottom portion of the deep trench is expanded to form a bottle shaped trench, and a buried plated is formed underneath the buried insulator layer. The dielectric spacer may be recessed during formation of a buried strap to form a graded thickness dielectric collar around the upper portion of an inner electrode. Alternately, the dielectric spacer may be removed prior to formation of a buried strap.
摘要翻译：用于SOI电容器的瓶形沟槽通过简单的处理顺序形成。在深沟槽的侧壁上形成具有可选的适形电介质扩散阻挡层的非保形介电层。采用各向同性蚀刻，从深沟槽的底部去除非共形电介质层，留下覆盖掩埋绝缘体层和顶部半导体层的侧壁的电介质间隔物。深沟槽的底部被膨胀以形成瓶形沟槽，并且在掩埋绝缘体层的下方形成埋入的电镀层。在形成掩埋带的过程中，电介质间隔物可以是凹陷的，以形成围绕内电极的上部的分级厚度的介质环。或者，可以在形成掩埋带之前去除电介质间隔物。

20. 发明申请

US20090289291A1 SOI DEEP TRENCH CAPACITOR EMPLOYING A NON-CONFORMAL INNER SPACER 失效
标题翻译： SOI深层电容器采用不合格的内部间隔器
公开(公告)号：US20090289291A1
公开(公告)日：2009-11-26
申请号：US12124186
申请日：2008-05-21
申请人： Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Geng Wang
发明人： Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Geng Wang
IPC分类号： H01L29/94 , H01L21/20
CPC分类号： H01L29/945 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L29/66181
摘要： A bottle shaped trench for an SOI capacitor is formed by a simple processing sequence. A non-conformal dielectric layer with an optional conformal dielectric diffusion barrier layer underneath is formed on sidewalls of a deep trench. Employing an isotropic etch, the non-conformal dielectric layer is removed from a bottom portion of the deep trench, leaving a dielectric spacer covering sidewalls of the buried insulator layer and the top semiconductor layer. The bottom portion of the deep trench is expanded to form a bottle shaped trench, and a buried plated is formed underneath the buried insulator layer. The dielectric spacer may be recessed during formation of a buried strap to form a graded thickness dielectric collar around the upper portion of an inner electrode. Alternately, the dielectric spacer may be removed prior to formation of a buried strap.
摘要翻译：用于SOI电容器的瓶形沟槽通过简单的处理顺序形成。在深沟槽的侧壁上形成具有可选的适形电介质扩散阻挡层的非保形介电层。采用各向同性蚀刻，从深沟槽的底部去除非共形电介质层，留下覆盖掩埋绝缘体层和顶部半导体层的侧壁的电介质间隔物。深沟槽的底部被膨胀以形成瓶形沟槽，并且在掩埋绝缘体层的下方形成埋入的电镀层。在形成掩埋带的过程中，电介质间隔物可以是凹陷的，以形成围绕内电极的上部的分级厚度的介质环。或者，可以在形成掩埋带之前去除电介质间隔物。

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