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11. 发明授权

US08284527B2 Magnetic heads having a graded domain control film and methods of manufacture thereof 有权
标题翻译：具有梯度域控制膜的磁头及其制造方法
公开(公告)号：US08284527B2
公开(公告)日：2012-10-09
申请号：US12957229
申请日：2010-11-30
申请人： Nobuo Yoshida , Masato Shiimoto , Kenichi Akita , Kan Yasui
发明人： Nobuo Yoshida , Masato Shiimoto , Kenichi Akita , Kan Yasui
IPC分类号： G11B5/39
CPC分类号： H01L43/08 , B82Y25/00 , G01R33/093 , G01R33/098 , G11B5/3912 , G11B5/398
摘要： A magnetic head, according to one embodiment, includes a sensor film, a sensor cap film provided above the sensor film, a pair of shields including an upper magnetic shield and a lower magnetic shield which serve as electrodes that pass current in a film thickness direction of the sensor film, a track insulating film contacting both sides of the sensor film in the track width direction, a graded domain control film arranged on both sides in the track width direction of the sensor film adjacent the track insulating film, and an element height direction insulating film positioned on an opposite side of the sensor film relative to an air-bearing surface, wherein an edge position of the element height direction insulating film adjacent the sensor film on the air-bearing surface side is substantially the same as an edge position of the sensor cap film in the element height direction.
摘要翻译：根据一个实施例的磁头包括传感器膜，设置在传感器膜上方的传感器盖膜，包括上磁屏蔽和下磁屏蔽的一对屏蔽件，其用作使电流在膜厚度方向上通过的电极传感器膜的传感器膜的两侧接触的轨道绝缘膜，布置在邻近轨道绝缘膜的传感器膜的轨道宽度方向两侧的梯度控制膜和元件高度相对于空气轴承表面定位在传感器膜的相对侧上的方向绝缘膜，其中与空气轴承表面侧相邻的传感器膜的元件高度方向绝缘膜的边缘位置与边缘位置基本相同传感器盖膜在元件高度方向上。

12. 发明申请

US20120026798A1 SEMICONDUCTOR NONVOLATILE MEMORY DEVICE 有权
标题翻译：半导体非易失性存储器件
公开(公告)号：US20120026798A1
公开(公告)日：2012-02-02
申请号：US13269425
申请日：2011-10-07
申请人： Digh HISAMOTO , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
发明人： Digh HISAMOTO , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
IPC分类号： G11C16/10
CPC分类号： G11C16/0425 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
摘要翻译：提供一种稳定运行半导体非易失性存储器件的操作方案。当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。因此，可以验证擦除状态，而不知道任何时变变化。此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

13. 发明授权

US08076709B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08076709B2
公开(公告)日：2011-12-13
申请号：US12873679
申请日：2010-09-01
申请人： Tetsuya Ishimaru , Digh Hisamoto , Kan Yasui , Shinichiro Kimura
发明人： Tetsuya Ishimaru , Digh Hisamoto , Kan Yasui , Shinichiro Kimura
IPC分类号： H01L29/792 , G11C16/04
CPC分类号： G11C16/0466 , H01L21/28282 , H01L29/66833 , H01L29/792
摘要： In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.
摘要翻译：在存储单元包括ONO膜的情况下，其包括用于电荷存储的氮化硅膜和位于氮化硅膜上方和下方的氧化膜; 在ONO电影上方的记忆门; 选择栅极，其经由ONO膜与存储栅的侧表面相邻; 位于选择门下方的栅极绝缘体; 源区; 和漏极区域，通过将BTBT产生的空穴注入氮化硅膜，同时向源极区域施加正电位，向存储栅极施加负电位，向选择栅极施加正电位，进行擦除操作，以及使电流从漏极区域流向源极区域，从而改善非易失性半导体存储器件的特性。

14. 发明授权

US08064261B2 Semiconductor nonvolatile memory device 有权
标题翻译：半导体非易失性存储器件
公开(公告)号：US08064261B2
公开(公告)日：2011-11-22
申请号：US12787158
申请日：2010-05-25
申请人： Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
发明人： Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/0425 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
摘要翻译：提供一种稳定运行半导体非易失性存储器件的操作方案。当在分裂栅结构的半导体非易失性存储器件中进行热孔注入时，使用不随时间变化的交叉点来验证热孔注入。因此，可以验证擦除状态，而不知道任何时变变化。此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

15. 发明授权

US07863131B2 Semiconductor device and manufacturing method for semiconductor device to reduce the lithography masks 有权
标题翻译：用于半导体器件的半导体器件和制造方法来减少光刻掩模
公开(公告)号：US07863131B2
公开(公告)日：2011-01-04
申请号：US11189078
申请日：2005-07-26
申请人： Kan Yasui , Digh Hisamoto , Tetsuya Ishimaru
发明人： Kan Yasui , Digh Hisamoto , Tetsuya Ishimaru
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , G11C16/0466 , H01L27/115 , H01L27/11519 , H01L27/11568 , H01L29/42344
摘要： Semiconductor device and manufacturing method for reducing the number of required lithography masks added to the nonvolatile memory in the standard CMOS process to shorten the production period and reduce costs. In a split-gate memory cell with silicided gate electrodes utilizing a sidewall structure, a separate auxiliary pattern is formed adjoining the selected gate electrodes. A contact is set on a wiring layer self-aligned by filling side-wall gates of polysilicon in the gap between the electrodes and auxiliary pattern. The contact may overlap onto the auxiliary pattern and device isolation region, in an optimal design considering the size of the occupied surface area. If the distance to the selected gate electrode is x, the ONO film deposit thickness is t, and the polysilicon film deposit thickness is d, then the auxiliary pattern may be separated just by a distance x such that x
摘要翻译：用于减少在标准CMOS工艺中添加到非易失性存储器中的所需光刻掩模的数量的半导体器件和制造方法，以缩短生产周期并降低成本。在具有利用侧壁结构的硅化栅电极的分裂栅极存储单元中，形成邻接所选择的栅电极的单独辅助图案。通过填充电极和辅助图案之间的间隙中的多晶硅的侧壁栅极，将接触设置在自对准的布线层上。考虑到占用的表面积的大小，接触可以以最佳设计重叠在辅助图案和设备隔离区域上。如果与选定的栅电极的距离为x，则ONO膜沉积厚度为t，多晶硅膜沉积厚度为d，则辅助图案可以仅分开距离x，使得x <2×（t + d ）。

16. 发明授权

US07671404B2 Fabrication method and structure of semiconductor non-volatile memory device 有权
标题翻译：半导体非易失性存储器件的制造方法和结构
公开(公告)号：US07671404B2
公开(公告)日：2010-03-02
申请号：US11589095
申请日：2006-10-30
申请人： Digh Hisamoto , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
发明人： Digh Hisamoto , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
IPC分类号： H01L29/94
CPC分类号： H01L27/11531 , H01L21/28282 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/42344 , H01L29/792
摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.
摘要翻译：提供具有良好写入/擦除特性的非易失性半导体存储器件。通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极氧化硅膜。存储器栅极通过层叠膜与选择栅极相邻。在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

17. 发明授权

US07636253B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07636253B2
公开(公告)日：2009-12-22
申请号：US12354867
申请日：2009-01-16
申请人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
发明人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
IPC分类号： G11C11/34
CPC分类号： H01L27/1157 , G11C16/0425 , H01L21/28282 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/0649 , H01L29/4234 , H01L29/42344 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
摘要翻译：半导体存储器阵列包括具有第一电荷存储层和第一非易失性存储单元的第一非易失性存储单元，第一非易失性存储单元与第一存储单元相邻，具有第二电荷存储层和第二栅电极。第一电极和第二电极在垂直于第一方向的第二方向上延伸，第一电极具有在第一方向上朝向第二电极延伸的第一接触部分，并且第二电极具有朝向第一电极的第二接触部分第一个方向第一和第二接触位置分别沿第二方向移动，第一电极和第一接触部分与第二电极和第二接触部分电气分离。

18. 发明申请

US20070201272A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070201272A1
公开(公告)日：2007-08-30
申请号：US11797164
申请日：2007-05-01
申请人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
发明人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
IPC分类号： G11C16/04
CPC分类号： H01L27/1157 , G11C16/0425 , H01L21/28282 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/0649 , H01L29/4234 , H01L29/42344 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
摘要翻译：半导体存储器阵列包括具有第一电荷存储层和第一非易失性存储单元的第一非易失性存储单元，第一非易失性存储单元与第一存储单元相邻，具有第二电荷存储层和第二栅电极。第一电极和第二电极在垂直于第一方向的第二方向上延伸，第一电极具有在第一方向上朝向第二电极延伸的第一接触部分，并且第二电极具有朝向第一电极的第二接触部分第一个方向第一和第二接触位置分别沿第二方向移动，第一电极和第一接触部分与第二电极和第二接触部分电气分离。

19. 发明授权

US06221773B1 Method for working semiconductor wafer 有权
标题翻译：半导体晶圆工作方法
公开(公告)号：US06221773B1
公开(公告)日：2001-04-24
申请号：US09254431
申请日：1999-03-09
申请人： Kan Yasui , Shigeo Moriyama , Katsuhiko Yamaguchi , Yoshio Homma
发明人： Kan Yasui , Shigeo Moriyama , Katsuhiko Yamaguchi , Yoshio Homma
IPC分类号： H01L21302
CPC分类号： H01L21/31053 , B24B7/228 , B24B37/04 , B24B37/042 , B24B37/08 , B24B53/017 , Y10S438/959
摘要： A method for processing semiconductor wafers, which provides planarized surface in a well controllable manner and with high accuracy by processing a film with uneven surface, formed over a semiconductor wafer, within the area of a working surface with a diameter larger than that of said semiconductor wafer by not more than two times, and by processing the film with a polishing liquid supplied from a supply unit disposed on a vertically arranged working surface is disclosed. Additionally, high quality dressing of the working surface can be easily performed by virtue of the smaller diameter of the working surface. Furthermore, the vertical arrangement of the working surface makes possible ready compatibility with semiconductor wafers of enlarged diameters.
摘要翻译：一种用于处理半导体晶片的方法，其在工作表面的直径大于所述半导体的直径的区域内，以半导体晶片形成在半导体晶片上，通过处理具有不平坦表面的膜，以良好可控的方式并且以高精度提供平坦化表面晶片不超过两次，并且通过用设置在垂直布置的工作表面上的供应单元供应的抛光液处理该膜。此外，通过工作表面的较小直径，可以容易地进行工作表面的高质量的修整。此外，工作表面的垂直布置使得可以准确地兼容扩大直径的半导体晶片。

20. 发明授权

US08319265B2 Semiconductor device with improved common source arrangement for adjacent non-volatile memory cells 有权
标题翻译：具有改进的用于相邻非易失性存储器单元的共同源排列的半导体器件
公开(公告)号：US08319265B2
公开(公告)日：2012-11-27
申请号：US12580289
申请日：2009-10-16
申请人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
发明人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
IPC分类号： H01L29/792
CPC分类号： H01L27/1157 , G11C16/0425 , H01L21/28282 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/0649 , H01L29/4234 , H01L29/42344 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
摘要翻译：半导体存储器阵列包括具有第一电荷存储层和第一非易失性存储单元的第一非易失性存储单元，第一非易失性存储单元与第一存储单元相邻，具有第二电荷存储层和第二栅电极。第一电极和第二电极在垂直于第一方向的第二方向上延伸，第一电极具有在第一方向上朝向第二电极延伸的第一接触部分，并且第二电极具有朝向第一电极的第二接触部分第一个方向第一和第二接触位置分别沿第二方向移动，第一电极和第一接触部分与第二电极和第二接触部分电气分离。

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