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11. 发明授权

US07737871B2 MCU with integrated voltage isolator to provide a galvanic isolation between input and output 有权
标题翻译： MCU具有集成电压隔离器，可在输入和输出之间提供电隔离
公开(公告)号：US07737871B2
公开(公告)日：2010-06-15
申请号：US12164998
申请日：2008-06-30
申请人： Ka Y. Leung , Donald E. Alfano , David P. Bresemann
发明人： Ka Y. Leung , Donald E. Alfano , David P. Bresemann
IPC分类号： H03M9/00
CPC分类号： H01L23/66 , H01L23/48 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2224/05554 , H01L2224/48095 , H01L2224/48137 , H01L2224/48247 , H01L2224/48257 , H01L2224/49171 , H01L2224/49175 , H01L2924/00014 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2224/45099
摘要： An integrated circuit comprises a first microcontroller unit located on a first die. The first microcontroller unit includes a first processing core for providing a parallel stream of data. A second microcontroller unit is located on a second die and includes a second processing core for receiving the parallel stream of data. Voltage isolation circuitry transmits data from the parallel data stream between the first microcontroller and the second microcontroller in a serial data stream and provides galvanic isolation between the first microcontroller unit and the second microcontroller unit.
摘要翻译：集成电路包括位于第一管芯上的第一微控制器单元。第一微控制器单元包括用于提供并行数据流的第一处理核心。第二微控制器单元位于第二管芯上，并且包括用于接收并行数据流的第二处理核。电压隔离电路以串行数据流从第一微控制器和第二微控制器之间的并行数据流传输数据，并且在第一微控制器单元和第二微控制器单元之间提供电隔离。

12. 发明授权

US07701685B2 Digital pulse width modulator with built-in protection functions for over current, over voltage and temperature 有权
标题翻译：数字脉宽调制器，内置保护功能，适用于过电流，过电压和温度
公开(公告)号：US07701685B2
公开(公告)日：2010-04-20
申请号：US11096043
申请日：2005-03-31
申请人： Kafai Leung , Ka Y. Leung , Donald E. Alfano
发明人： Kafai Leung , Ka Y. Leung , Donald E. Alfano
IPC分类号： H02H3/08
CPC分类号： H03K7/08 , H02M1/32 , H02M3/157
摘要： An apparatus for providing over current protection for a digital pulse width modulator is disclosed. The apparatus includes first logic circuitry for generating a primary interrupt indicating that a detected output current is greater than a threshold current. Second logic circuitry generates a secondary input responsive to the occurrence to the primary interrupt for a predetermined number of times.
摘要翻译：公开了一种用于为数字脉宽调制器提供过流保护的装置。该装置包括用于产生指示检测到的输出电流大于阈值电流的主中断的第一逻辑电路。第二逻辑电路响应于主中断的发生预定次数产生次级输入。

13. 发明授权

US07613901B2 Comparators in IC with programmably controlled positive / negative hysteresis level and open-drain / push-pull output coupled to crossbar switch or rising / falling edge interrupt generation 有权
标题翻译： IC中的比较器具有可编程控制的正/负滞后电平和开漏/推挽输出，连接到交叉开关或上升/下降沿中断产生
公开(公告)号：US07613901B2
公开(公告)日：2009-11-03
申请号：US11694629
申请日：2007-03-30
申请人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas R. Holberg
发明人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas R. Holberg
IPC分类号： G06F19/00 , H03K5/22
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： An integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A plurality of comparators perform compare operations within the integrated circuit package. At least one control register is associated with each of the plurality of comparators, and each of the plurality of comparators are software programmable to control a hysteresis of the comparators responsive to control bits established in the at least one control register of the comparator by the processing core. An amount of positive hysteresis is programmed via a first group of the control bits and an amount of negative hysteresis is programmed via a second group of the control bits.
摘要翻译：集成电路封装包括用于对一组指令进行操作以执行预定义的处理的处理核心。多个比较器执行集成电路封装内的比较操作。至少一个控制寄存器与多个比较器中的每个比较器相关联，并且多个比较器中的每一个可软件编程以响应于通过处理在比较器的至少一个控制寄存器中建立的控制位来控制比较器的滞后核心。通过第一组控制位来编程正滞后量，经由第二组控制位来编程负滞后量。

14. 发明授权

US07504900B2 Integrated circuit package including programmable oscillators 有权
标题翻译：集成电路封装，包括可编程振荡器
公开(公告)号：US07504900B2
公开(公告)日：2009-03-17
申请号：US11694624
申请日：2007-03-30
申请人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alan Storvik , Paul Highley , Douglas R. Holberg
发明人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alan Storvik , Paul Highley , Douglas R. Holberg
IPC分类号： G06F1/04 , H03B5/00 , H03B5/12 , H03B5/24 , H03B5/36
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： An integrated circuit package includes a processing core and an internal oscillator. The processing core operates on a set of instructions to carry out predefined processes. The internal oscillator provides a system clock for the integrated circuit package. The internal oscillator has associated therewith an internal control register for controlling the operation of the internal oscillator responsive to control bits of the internal oscillator controlled by the processing core.
摘要翻译：集成电路封装包括处理核心和内部振荡器。处理核心通过一组指令来执行预定义的过程。内部振荡器为集成电路封装提供系统时钟。内部振荡器具有与其相关联的内部控制寄存器，用于响应于由处理核心控制的内部振荡器的控制位来控制内部振荡器的操作。

15. 发明授权

US07456621B2 Digital controller based power factor correction circuit 失效
标题翻译：基于数字控制器的功率因数校正电路
公开(公告)号：US07456621B2
公开(公告)日：2008-11-25
申请号：US11382009
申请日：2006-05-05
申请人： Ka Y. Leung , Donald E. Alfano , Ross Martin Fosler
发明人： Ka Y. Leung , Donald E. Alfano , Ross Martin Fosler
IPC分类号： G05F1/40
CPC分类号： H02M3/157 , H02M1/42 , H03K17/0822 , Y02B70/12
摘要： A power factor correction circuit utilizes a digital controller string comprised of an analog-to-digital converter, which is input to a digital compensator followed by a pulse width modulation circuit for generating a switching pulse. The loop current in a regulator circuit such as a boost regulator is sensed and input to one side of a differential analog-to-digital converter, the other side thereof providing a digital reference current. This digital reference current is derived from comparing the input AC voltage to the regulator with the DC output voltage and processing these two voltages with a PFC algorithm to provide this reference voltage.
摘要翻译：功率因数校正电路利用由模数转换器组成的数字控制器串，其输入到数字补偿器，随后是用于产生开关脉冲的脉宽调制电路。调节器电路（例如升压调节器）中的回路电流被感测并输入到差分模数转换器的一侧，其另一侧提供数字参考电流。该数字参考电流是通过将输入AC电压与调节器与直流输出电压进行比较而得到的，并使用PFC算法处理这两个电压以提供该参考电压。

16. 发明授权

US07738568B2 Multiplexed RF isolator 有权
标题翻译：多路复用RF隔离器
公开(公告)号：US07738568B2
公开(公告)日：2010-06-15
申请号：US11772162
申请日：2007-06-30
申请人： Donald E. Alfano , Brett Etter , Timothy Dupuis
发明人： Donald E. Alfano , Brett Etter , Timothy Dupuis
IPC分类号： H04B3/00
CPC分类号： H01L23/66 , H01L23/49503 , H01L23/4952 , H01L23/49575 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05554 , H01L2224/48095 , H01L2224/48137 , H01L2224/48247 , H01L2224/48464 , H01L2224/49171 , H01L2224/49175 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/1204 , H01L2924/12041 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H04B3/542 , H04B3/548 , H04B3/56 , H04B2203/542 , H04L25/0266 , H01L2224/45099 , H01L2924/00012 , H01L2924/00
摘要： A system for providing multiple communication channels over a single voltage isolation link includes first circuitry for multiplexing a plurality of digital data inputs from a plurality of communication channels onto the single voltage isolation link. Second circuitry de-multiplexes the plurality of digital data inputs from the single voltage isolation link to the plurality of communication channels. An RF isolator is used for providing the single voltage isolation link.
摘要翻译：用于在单个电压隔离链路上提供多个通信信道的系统包括用于将来自多个通信信道的多个数字数据输入复用到单电压隔离链路上的第一电路。第二电路将多个数字数据输入从单电压隔离链路解复用到多个通信信道。 RF隔离器用于提供单电压隔离链路。

17. 发明授权

US07577223B2 Multiplexed RF isolator circuit 有权
标题翻译：多路复用RF隔离电路
公开(公告)号：US07577223B2
公开(公告)日：2009-08-18
申请号：US11772186
申请日：2007-06-30
申请人： Donald E. Alfano , Brett Etter , Timothy Dupuis
发明人： Donald E. Alfano , Brett Etter , Timothy Dupuis
IPC分类号： H04L7/04
CPC分类号： H01L23/66 , H01L23/49503 , H01L23/4952 , H01L23/49575 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05554 , H01L2224/48095 , H01L2224/48137 , H01L2224/48247 , H01L2224/48464 , H01L2224/49171 , H01L2224/49175 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/1204 , H01L2924/12041 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H04B3/542 , H04B3/56 , H04B2203/542 , H04L25/0266 , H01L2224/45099 , H01L2924/00012 , H01L2924/00
摘要： An integrated circuit isolator for providing data transfer of digital data signals across a voltage isolation barrier includes an integrated circuit package having a first plurality of input data pins on one side of the isolation barrier and a corresponding plurality of output data pins on the other side of the isolation boundary. First circuitry is associated with the first plurality of input data pins and second circuitry is associated with the plurality of output data pins. A communications interface provides across the voltage isolation barrier a first communications channel for communicating data from the first circuitry to the second circuitry and a second communications channel for communicating synchronization clock data from the first circuitry to the second circuitry. The first circuitry is operable to communicate information from input digital data overlapping each other in time and received on two or more of the associated first plurality of input data pins across the first communications channel and to communicate the synchronization clock signal across the second communications channel. The second circuitry is operable to receive the communicated data from the first circuitry and reconstruct the data for output on the ones of the plurality of output data pins corresponding to the two or more of the associated plurality of input data pins from which the data was communicated responsive to the synchronization clock signal.
摘要翻译：一种用于在电压隔离屏障上提供数字数据信号的数据传输的集成电路隔离器包括：集成电路封装，其具有在隔离屏障的一侧上的第一多个输入数据引脚和在另一侧的相应的多个输出数据引脚隔离边界。第一电路与第一组多个输入数据引脚相关联，第二电路与多个输出数据引脚相关联。通信接口在电压隔离屏障上提供用于将数据从第一电路传送到第二电路的第一通信信道和用于将同步时钟数据从第一电路传送到第二电路的第二通信信道。第一电路可操作以从时间上彼此重叠的输入数字数据传送信息，并在第一通信信道上的相关联的第一多个输入数据引脚中的两个或更多个上接收信号，并且跨越第二通信信道传送同步时钟信号。第二电路可操作以从第一电路接收所传送的数据，并且重构数据以输出与多个输入数据引脚相对应的多个输出数据引脚中的两个或多个相关联的多个输入数据引脚，数据从其传送响应于同步时钟信号。

18. 发明授权

US08861229B2 Isolator circuit including a voltage regulator 有权
标题翻译：隔离器电路包括一个稳压器
公开(公告)号：US08861229B2
公开(公告)日：2014-10-14
申请号：US12129039
申请日：2008-05-29
申请人： Donald E. Alfano , Timothy J. Dupuis , Zhiwei Dong , Brett E. Etter
发明人： Donald E. Alfano , Timothy J. Dupuis , Zhiwei Dong , Brett E. Etter
IPC分类号： H02M3/335 , H02M3/156
CPC分类号： H03K17/691 , H03K17/7955
摘要： An apparatus includes a regulator circuit that generates a voltage in response to an input current being supplied to an input terminal and functional circuitry, powered by the voltage generated by the regulator circuit. The functional circuitry, e.g., an oscillator, generates a signal using the generated voltage, the signal indicative that the current is being supplied to the apparatus. The signal can be provided over an isolation link to provide a control signal for controlling a high voltage driver circuit.
摘要翻译：一种装置包括调节器电路，其响应于输入电流产生电压，该输入电流被提供给由调节器电路产生的电压供电的输入端子和功能电路。功能电路，例如振荡器，使用所产生的电压产生信号，该信号指示电流被提供给设备。信号可以通过隔离链路提供，以提供用于控制高电压驱动器电路的控制信号。

19. 发明授权

US06839795B1 Priority cross-bar decoder 有权
标题翻译：优先交叉条解码器
公开(公告)号：US06839795B1
公开(公告)日：2005-01-04
申请号：US09584308
申请日：2000-05-31
申请人： Kenneth W. Fernald , Danny J. Allred , Donald E. Alfano
发明人： Kenneth W. Fernald , Danny J. Allred , Donald E. Alfano
IPC分类号： H04Q3/52 , G06F13/00
CPC分类号： H04Q3/52 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13103 , H04Q2213/1325
摘要： A matrix of routing cells forming a cross-bar decoder (70). Signal triplets (84, 86, 88) coupled to the cross-bar decoder (70) are assigned a priority. A register (50) provide outputs to the cross-bar decoder (70) to either activate or deactivate routing of the triplet signals (84, 86,88) through the cross-bar decoder (70). The routing cells (72-82) are arranged in a matrix of columns and rows, where the triplet signals are applied to the row routing cells (72, 74, 76) and are extracted at the column routing cells (76, 80, 82). When a routing cell in a row is enabled to couple signals to an output, it disables all other lower priority routing cells in its column so that they cannot route signals to that output. Based on the automatic disabling of routing cells by others, the signals ripple through the cross-bar decoder (70) until all high priority I/O pins are used. The outputs of the cross-bar decoder (70) are coupled to respective I/O pins (170, 172, 174) by way of respective driver circuits (212, 216, 236).
摘要翻译：形成交叉条形码解码器（70）的路由信元的矩阵。耦合到交叉条形码解码器（70）的信号三元组（84,86,88）被赋予优先权。寄存器（50）向交叉条形码解码器（70）提供输出以通过交叉条形码解码器（70）来激活或去激活三联信号（84,88,88）的路由。路由单元（72-82）被布置成列和行的矩阵，其中三元组信号被施加到行路由单元（72,74,76），并且在列路由单元（76,80,82）处被提取）。当一行中的路由单元被使能以将信号耦合到输出时，它将禁用其列中的所有其他较低优先级的路由单元，使得它们不能将信号路由到该输出。基于其他路由单元的自动禁用，通过交叉条形码解码器（70）的信号直到所有高优先级I / O引脚使用。横杆解码器（70）的输出通过相应的驱动器电路（212,216,236）耦合到相应的I / O引脚（170,172,174）。

20. 发明授权

US6122284A Multidrop analog signal bus 失效
标题翻译：多点模拟信号总线
公开(公告)号：US6122284A
公开(公告)日：2000-09-19
申请号：US889109
申请日：1997-07-07
申请人： Ali Tasdighi , Joseph J. Judkins, III , Chuong Nguyen , Donald E. Alfano
发明人： Ali Tasdighi , Joseph J. Judkins, III , Chuong Nguyen , Donald E. Alfano
IPC分类号： H04Q11/00
CPC分类号： H04Q11/04
摘要： In the preferred embodiment, the outputs of a plurality of analog signal generators are connected to a single wire (the analog bus). Each analog signal generator is addressable by a unique code provided to its respective address input terminals. A host controller selectively addresses only one of the analog signal generators such that an output of only one of the analog signal generators is applied to the analog bus at a time. In this manner, a single wire may be used to transmit a plurality of analog signals to a receiver. In one embodiment, the receiver is a MUX having an output connected to an ADC.
摘要翻译：在优选实施例中，多个模拟信号发生器的输出端连接到单线（模拟总线）。每个模拟信号发生器可通过提供给其相应地址输入端的唯一代码寻址。主机控制器仅选择性地仅寻址模拟信号发生器中的一个，使得仅一个模拟信号发生器的输出一次被施加到模拟总线。以这种方式，可以使用单根线将多个模拟信号发送到接收机。在一个实施例中，接收器是具有连接到ADC的输出的MUX。

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