专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07352037B2 Semiconductor device and random access memory having single gate electrode corresponding to a pair of channel regions 有权
标题翻译：具有对应于一对通道区域的单个栅电极的半导体器件和随机存取存储器
公开(公告)号：US07352037B2
公开(公告)日：2008-04-01
申请号：US11393750
申请日：2006-03-31
申请人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park , Eun-Hong Lee , Jae-woong Hyun , Jung-hoon Lee , Sung-jae Byun
发明人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park , Eun-Hong Lee , Jae-woong Hyun , Jung-hoon Lee , Sung-jae Byun
IPC分类号： H01L29/94
CPC分类号： H01L29/66795 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L27/11507 , H01L27/2436 , H01L29/785
摘要： A semiconductor device may include at least one pair of fins on a semiconductor substrate. A channel region may be formed in each fin. The semiconductor device may further include a gate electrode corresponding to each pair of channel regions, a source contact plug electrically connected to each of at least one source formed on a respective fin concurrently, and a drain contact plug electrically connected to each of at least one drain formed on a respective fin concurrently.
摘要翻译：半导体器件可以包括半导体衬底上的至少一对散热片。可以在每个鳍中形成沟道区。半导体器件还可以包括对应于每对沟道区的栅电极，同时电连接到形成在相应散热片上的至少一个源中的每一个的源极接触插塞以及电连接到至少一个漏斗同时形成在相应的翅片上。

12. 发明申请

US20090280645A1 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090280645A1
公开(公告)日：2009-11-12
申请号：US12385982
申请日：2009-04-27
申请人： Jung-hoon Lee , Hong-jae Shin , Seo-woo Nam , Sae-il Son , Sang-doo Kim , Jung-deog Lee , Sang-wook Kwon
发明人： Jung-hoon Lee , Hong-jae Shin , Seo-woo Nam , Sae-il Son , Sang-doo Kim , Jung-deog Lee , Sang-wook Kwon
IPC分类号： H01L21/3205
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L29/665 , H01L29/7843
摘要： Provided is a method of fabricating a semiconductor device including a dual suicide process. The method may include sequentially siliciding and stressing a first MOS region, and sequentially siliciding and stressing a second MOS region after siliciding and stressing the first MOS region, the second MOS region being a different type than the first MOS region.
摘要翻译：提供一种制造包括双重自杀处理的半导体器件的方法。该方法可以包括顺序硅化和应力第一MOS区，并且在硅化和应力第一MOS区之后，依次硅化和应力第二MOS区，第二MOS区是与第一MOS区不同的类型。

13. 发明申请

US20080067612A1 Semiconductor Device Including Nickel Alloy Silicide Layer Having Uniform Thickness and Method of Manufacturing the Same 审中-公开
标题翻译：包括具有均匀厚度的镍合金硅化物层的半导体器件及其制造方法
公开(公告)号：US20080067612A1
公开(公告)日：2008-03-20
申请号：US11775089
申请日：2007-07-09
申请人： Sun Jung Lee , Bong-seok Suh , Hong-jae Shin , Kee-young Jun , Jung-hoon Lee
发明人： Sun Jung Lee , Bong-seok Suh , Hong-jae Shin , Kee-young Jun , Jung-hoon Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/324 , H01L21/28052 , H01L21/28518 , H01L21/288 , H01L29/165 , H01L29/665 , H01L29/66636 , H01L29/7833
摘要： A semiconductor device including a nickel alloy silicide layer having a uniform thickness includes isolation regions formed in a substrate, gate electrodes respectively formed on the substrate between the isolation regions, source/drain regions respectively formed between the gate electrodes and the isolation regions, spacers formed on lateral surfaces of the gate electrodes, and a nickel alloy silicide layer formed on upper portions of the source/drain regions.
摘要翻译：包括具有均匀厚度的镍合金硅化物层的半导体器件包括形成在衬底中的隔离区域，分别形成在隔离区域之间的衬底上的栅电极，分别形成在栅极电极和隔离区域之间的源极/漏极区域，形成间隔物在栅电极的侧表面上形成的镍合金硅化物层和形成在源/漏区上部的镍合金硅化物层。

14. 发明申请

US20070284632A1 Non-volatile memory device and a method of fabricating the same 有权
公开(公告)号：US20070284632A1
公开(公告)日：2007-12-13
申请号：US11709057
申请日：2007-02-22
申请人： Won-joo Kim , Yoon-dong Park , Jung-hoon Lee
发明人： Won-joo Kim , Yoon-dong Park , Jung-hoon Lee
IPC分类号： H01L29/00
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11519 , H01L29/42332 , H01L29/792
摘要： A non-volatile memory device and a method of fabricating the same are provided. A non-volatile memory device may include a semiconductor substrate including a body and at least one pair of fins vertically protruding from the body and spaced apart from each other, and at least one control gate electrode on at least portions of outer side surfaces of the at least one pair of fins and extending onto top portions of the at least one pair of fins on an angle with the at least one pair of fins. The non-volatile memory device may further include at least one pair of gate insulating layers between the at least one control gate electrode and the at least one pair of fins, and at least one pair of storage node layers between the at least one pair of gate insulating layers and at least a portion of the at least one control gate electrode. The at least one control gate electrode may extend onto top portions of the at least one pair of fins in a zigzag fashion.

15. 发明申请

US20060097306A1 Multi bits flash memory device and method of operating the same 失效
公开(公告)号：US20060097306A1
公开(公告)日：2006-05-11
申请号：US11249393
申请日：2005-10-14
申请人： Won-joo Kim , Yoon-dong Park , Eun-hong Lee , Sun-ae Seo , Sang-min Shin , Jung-hoon Lee , Seung-hyuk Chang
发明人： Won-joo Kim , Yoon-dong Park , Eun-hong Lee , Sun-ae Seo , Sang-min Shin , Jung-hoon Lee , Seung-hyuk Chang
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： G11C11/5621 , B82Y10/00 , G11C11/5607 , G11C11/5628 , G11C11/5657 , G11C13/025 , H01L21/28273 , H01L21/28282 , H01L21/28291 , H01L29/0692 , H01L29/4232 , H01L29/7923
摘要： A multi bits flash memory device and a method of operating the same are disclosed. The multi bits flash memory device includes: a stacked structure including: a first active layer with a mesa-like form disposed on a substrate; a second active layer, having a different conductivity type from the first active layer, formed on the first active layer; an active interlayer isolation layer interposed between the first active layer and the second active layer such that the first active layer is electrically isolated from the second active layer; a common source and a common drain formed on a pair of opposite side surfaces of the stacked structure; a common first gate and a common second gate formed on the other pair of opposite side surfaces of the stacked structure; a tunnel dielectric layer interposed between the first and second gates and the first and second active layers; and a charge trap layer, storing charges that tunnel through the tunnel dielectric layer, interposed between the tunnel dielectric layer and the first and second gates.

16. 发明授权

US08293654B2 Nanowire memory device and method of manufacturing the same 有权
标题翻译：纳米线记忆装置及其制造方法
公开(公告)号：US08293654B2
公开(公告)日：2012-10-23
申请号：US13425807
申请日：2012-03-21
申请人： Jin-gyoo Yoo , Cheol-soon Kim , Jung-hoon Lee
发明人： Jin-gyoo Yoo , Cheol-soon Kim , Jung-hoon Lee
IPC分类号： H01L21/308
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/16 , H01L51/0048 , Y10S977/943
摘要： A nanowire memory device and a method of manufacturing the same are provided. A memory device includes: a substrate; a first electrode formed on the substrate; a first nanowire extending from an end of the first electrode; a second electrode formed over the first electrode to overlap the first electrode; and a second nanowire extending from an end of the second electrode corresponding to the end of the first electrode in the same direction as the first nanowire, wherein an insulating layer exists between the first and second electrodes.
摘要翻译：提供了一种纳米线存储器件及其制造方法。存储器件包括：衬底; 形成在所述基板上的第一电极; 从所述第一电极的端部延伸的第一纳米线; 形成在所述第一电极上以与所述第一电极重叠的第二电极; 以及从与第一电极的端部对应的第二电极的端部沿与第一纳米线相同的方向延伸的第二纳米线，其中在第一和第二电极之间存在绝缘层。

17. 发明申请

US20100320564A1 NANOWIRE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：纳米存储器件及其制造方法
公开(公告)号：US20100320564A1
公开(公告)日：2010-12-23
申请号：US12872835
申请日：2010-08-31
申请人： Jin-gyoo Yoo , Cheol-soon Kim , Jung-hoon Lee
发明人： Jin-gyoo Yoo , Cheol-soon Kim , Jung-hoon Lee
IPC分类号： H01L29/86 , H01L21/02
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/16 , H01L51/0048 , Y10S977/943
摘要： A nanowire memory device and a method of manufacturing the same are provided. A memory device includes: a substrate; a first electrode formed on the substrate; a first nanowire extending from an end of the first electrode; a second electrode formed over the first electrode to overlap the first electrode; and a second nanowire extending from an end of the second electrode corresponding to the end of the first electrode in the same direction as the first nanowire, wherein an insulating layer exists between the first and second electrodes.
摘要翻译：提供了一种纳米线存储器件及其制造方法。存储器件包括：衬底; 形成在所述基板上的第一电极; 从所述第一电极的端部延伸的第一纳米线; 形成在所述第一电极上以与所述第一电极重叠的第二电极; 以及从与第一电极的端部对应的第二电极的端部沿与第一纳米线相同的方向延伸的第二纳米线，其中在第一和第二电极之间存在绝缘层。

18. 发明授权

US07821813B2 Nanowire memory device and method of manufacturing the same 有权
标题翻译：纳米线记忆装置及其制造方法
公开(公告)号：US07821813B2
公开(公告)日：2010-10-26
申请号：US11714826
申请日：2007-03-07
申请人： Jin-gyoo Yoo , Cheol-soon Kim , Jung-hoon Lee
发明人： Jin-gyoo Yoo , Cheol-soon Kim , Jung-hoon Lee
IPC分类号： G11C11/50
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/16 , H01L51/0048 , Y10S977/943
摘要： A nanowire memory device and a method of manufacturing the same are provided. A memory device includes: a substrate; a first electrode formed on the substrate; a first nanowire extending from an end of the first electrode; a second electrode formed over the first electrode to overlap the first electrode; and a second nanowire extending from an end of the second electrode corresponding to the end of the first electrode in the same direction as the first nanowire, wherein an insulating layer exists between the first and second electrodes.
摘要翻译：提供了一种纳米线存储器件及其制造方法。存储器件包括：衬底; 形成在所述基板上的第一电极; 从所述第一电极的端部延伸的第一纳米线; 形成在所述第一电极上以与所述第一电极重叠的第二电极; 以及从与第一电极的端部对应的第二电极的端部沿与第一纳米线相同的方向延伸的第二纳米线，其中在第一和第二电极之间存在绝缘层。

19. 发明申请

US20080151631A1 Non-volatile memory device and method of operating the same 失效
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20080151631A1
公开(公告)日：2008-06-26
申请号：US11980358
申请日：2007-10-31
申请人： Jae-woong Hyun , Kyu-charn Park , Yoon-dong Park , Won-joo Kim , Young-gu Jin , Suk-pil Kim , Kyoung-lae Cho , Jung-hoon Lee , Seung-hwan Song
发明人： Jae-woong Hyun , Kyu-charn Park , Yoon-dong Park , Won-joo Kim , Young-gu Jin , Suk-pil Kim , Kyoung-lae Cho , Jung-hoon Lee , Seung-hwan Song
IPC分类号： G11C16/06 , H01L29/788
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L27/1203
摘要： A highly integrated non-volatile memory device and a method of operating the non-volatile memory device are provided. The non-volatile memory device includes a semiconductor layer. A plurality of upper control gate electrodes are arranged above the semiconductor layer. A plurality of lower control gate electrodes are arranged below the semiconductor layer, and the plurality of upper control gate electrodes and the plurality of lower control gate electrodes are disposed alternately. A plurality of upper charge storage layers are interposed between the semiconductor layer and the upper control gate electrodes. A plurality of lower charge storage layers are interposed between the semiconductor layer and the lower control gate electrodes.
摘要翻译：提供高度集成的非易失性存储器件和操作非易失性存储器件的方法。非易失性存储器件包括半导体层。多个上控制栅电极设置在半导体层的上方。多个下部控制栅电极配置在半导体层的下方，多个上部控制栅极电极和多个下部控制栅极电极交替配置。多个上电荷存储层插入在半导体层和上控制栅电极之间。多个下电荷存储层插入在半导体层和下控制栅电极之间。

20. 发明申请

US20070298600A1 Method of Fabricating Semiconductor Device and Semiconductor Device Fabricated Thereby 审中-公开
标题翻译：由此制造半导体器件和半导体器件的方法
公开(公告)号：US20070298600A1
公开(公告)日：2007-12-27
申请号：US11425841
申请日：2006-06-22
申请人： Bong-seok Suh , Hong-jae Shin , Sun-jung Lee , Min-chul Sun , Jung-hoon Lee
发明人： Bong-seok Suh , Hong-jae Shin , Sun-jung Lee , Min-chul Sun , Jung-hoon Lee
IPC分类号： H01L21/3205
CPC分类号： H01L21/76846
摘要： A method of fabricating a semiconductor device and a semiconductor device fabricated thereby. The method of fabricating the semiconductor device includes forming gate electrodes on a semiconductor substrate; forming source/drain regions within the semiconductor substrate so as to be located at both sides of each of the gate electrodes; forming a nickel silicide layer on surfaces of the gate electrodes and the source/drain regions by evaporating nickel or nickel alloy on the semiconductor substrate formed with the gate electrodes and the source/drain regions and then performing a thermal process on the nickel or the nickel alloy; forming an interlayer insulating layer, which is formed with contact holes through which a surface of the nickel silicide layer is exposed, on a surface obtained after the above processes have been performed; forming an ohmic layer by evaporating a refractory metal conformably along the contact holes, the refractory metal being converted to silicide at a temperature of 500° C. or more; forming a diffusion barrier on the ohmic layer conformably along the contact holes; and forming a metal layer by burying a metal material within the contact holes.
摘要翻译：一种制造半导体器件的方法及其制造的半导体器件。制造半导体器件的方法包括在半导体衬底上形成栅电极; 在半导体衬底内形成源/漏区，以便位于每个栅电极的两侧; 通过在形成有栅电极和源极/漏极区域的半导体衬底上蒸发镍或镍合金，然后在镍或镍上进行热处理，在栅电极和源/漏区的表面上形成硅化镍层合金; 形成层间绝缘层，所述层间绝缘层在进行上述处理后得到的表面上形成有暴露所述镍硅化物层的表面的接触孔; 通过沿着接触孔顺应蒸发难熔金属形成欧姆层，难熔金属在500℃或更高的温度下转化为硅化物; 在欧姆层上沿着接触孔顺应地形成扩散阻挡层; 以及通过在接触孔内埋入金属材料来形成金属层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式